參數(shù)資料
型號(hào)： M41T65Q6F
廠商： STMICROELECTRONICS
元件分類： 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述： 1 TIMER(S), REAL TIME CLOCK, QCC16
封裝： 3 X 3 MM, LEAD FREE, QFN-16
文件頁(yè)數(shù)： 4/40頁(yè)
文件大?。?/td> 707K
代理商： M41T65Q6F
Operation
M41T62/63/64/65
Doc ID 10397 Rev 12
2
Operation
The M41T6x clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 16 bytes
contained in the device can then be accessed sequentially in the following order:
●
1st byte: tenths/hundredths of a second register
●
2nd byte: seconds register
●
3rd byte: minutes register
●
4th byte: hours register
●
5th byte: square wave/day register
●
6th byte: date register
●
7th byte: century/month register
●
8th byte: year register
●
9th byte: calibration register
●
10th byte: watchdog register
●
11th - 15th bytes: alarm registers
●
16th byte: flags register
2.1
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bi-
directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
●
Data transfer may be initiated only when the bus is not busy.
●
During data transfer, the data line must remain stable whenever the clock line is high.
●
Changes in the data line, while the clock line is high, will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain high.
2.1.2
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
2.1.3
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.
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