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參數(shù)資料
| 型號(hào)： | M41T64Q6F |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取 |
| 英文描述： | 1 TIMER(S), REAL TIME CLOCK, QCC16 |
| 封裝： | 3 X 3 MM, LEAD FREE, QFN-16 |
| 文件頁(yè)數(shù)： | 28/40頁(yè) |
| 文件大小： | 707K |
| 代理商： | M41T64Q6F |
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DC and AC parameters
M41T62/63/64/65
Doc ID 10397 Rev 12
Table 17.
Oscillator characteristics
Figure 25. Bus timing requirements sequence
Table 18.
AC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VSTA
Oscillator start voltage
≤ 10 seconds
1.5
V
tSTA
Oscillator start time
VCC = 3.0 V
1
s
Cg
XIN capacitance
12
pF
Cd
XOUT capacitance
12
pF
IC-to-IC frequency variation (1)
1.
Reference value. TA = 25 °C, VCC = 3.0 V, CMJ-145 (CL = 6 pF, 32,768 Hz) manufactured by Citizen,
CL = Cg Cd / (Cg + Cd).
–10
+10
ppm
Sym
Parameter(1)
1.
Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 1.3 to 4.4 V (except where noted).
Min
Max
Units
fSCL
SCL clock frequency
0
400
kHz
tLOW
Clock low period
1.3
s
tHIGH
Clock high period
600
ns
tR
SDA and SCL rise time
300
ns
tF
SDA and SCL fall time
300
ns
tHD:STA
START condition hold time
(after this period the first clock pulse is generated)
600
ns
tSU:STA
START condition setup time
(only relevant for a repeated start condition)
600
ns
tSU:DAT
(2)
2.
Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling
edge of SCL.
Data setup time
100
ns
tHD:DAT
Data hold time
0
s
tSU:STO
STOP condition setup time
600
ns
tBUF
Time the bus must be free before a new
transmission can start
1.3
s
trec
Watchdog output pulse width
96
98
ms
AI00589
SDA
P
tSU:STO
tSU:STA
tHD:STA
SR
SCL
tSU:DAT
tF
tHD:DAT
tR
tHIGH
tLOW
tHD:STA
tBUF
S
P
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