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參數(shù)資料
| 型號(hào)： | M41T256YSH |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Hook-Up Wire; Conductor Size AWG:24; No. Strands x Strand Size:Solid; Jacket Color:Brown; Approval Bodies:UL, CSA; Approval Categories:UL AWM Style 1061; CSA AWM; Conductor Material:Copper; Jacket Material:Polyvinylchloride (PVC) RoHS Compliant: Yes |
| 中文描述： | 256千位32K的x8串行實(shí)時(shí)時(shí)鐘 |
| 文件頁數(shù)： | 12/26頁 |
| 文件大小： | 363K |
| 代理商： | M41T256YSH |
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M41T256Y
12/26
READ Mode
In this mode the master reads the M41T256Y
slave after setting the slave address (see Figure
11, page 12). Following the WRITE Mode Control
Bit (R/W=0) and the Acknowledge Bit, the byte ad-
dresses A(0) and A(1) are written to the on-chip
address pointer (MSB of address byte A(0) is a
“Don’t care”). Next the START condition and slave
address are repeated followed by the READ Mode
Control Bit (R/W=1). At this point the master trans-
mitter becomes the master receiver. The data byte
which was addressed will be transmitted and the
master receiver will send an acknowledge bit to
the slave transmitter. The address pointer is only
incremented on reception of an Acknowledge
Clock. The M41T256Y slave transmitter will now
place the data byte at address An+1 on the bus,
the master receiver reads and acknowledges the
new byte and the address pointer is incremented
to An+2.
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter (see Figure 12,
page 13).
Note:
Address pointer will wrap around from max-
imum address to minimum address if consecutive
READ or WRITE cycles are performed.
An alternate READ Mode may also be implement-
ed whereby the master reads the M41T256Y slave
without first writing to the (volatile) address point-
er. The first address that is read is the last one
stored in the pointer (see Figure 13, page 13).
WRITE Mode
In this mode the master transmitter transmits to
the M41T256Y slave receiver. Bus protocol is
shown in Figure Figure 14, page 13. Following the
START condition and slave address, a logic '0' (R/
W=0) is placed on the bus and indicates to the ad-
dressed device that byte addresses A(0) and A(1)
will follow and is to be written to the on-chip ad-
dress pointer (MSB of address byte A(0) is a
“Don’t care”). The data byte to be written to the
memory is strobed in next and the internal address
pointer is incremented to the next memory location
within the RAM on the reception of an acknowl-
edge bit. The M41T256Y slave receiver will send
an acknowledge bit to the master transmitter after
it has received the slave address (see Figure 11,
page 12) and again after it has received each ad-
dress byte.
Figure 11. Slave Address Location
Note: The most significant bit is sent first.
AI00602
R/W
SLAVE ADDRESS
START
A
0
1
0
0
0
1
1
M
L
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| M41T256Y | 256 Kbit 32K x8 SERIAL RTC |
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| M41T256YMH | 256 Kbit 32K x8 SERIAL RTC |
| M41T256YMT | 256 Kbit 32K x8 SERIAL RTC |
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