參數(shù)資料
型號: M41T256YMT7TR
廠商: 意法半導體
英文描述: RCA-F TO RCA-F COUPLER
中文描述: 256千位32K的x8串行實時時鐘
文件頁數(shù): 18/26頁
文件大?。?/td> 363K
代理商: M41T256YMT7TR
M41T256Y
18/26
Power-on Reset
The M41T256Y continuously monitors V
CC
. When
V
CC
falls to the power fail detect trip point, the RST
pulls low (open drain) and remains low on power-
up for t
REC
after V
CC
passes V
PFD
(max). The RST
pin is an open drain output and an appropriate
pull-up resistor should be chosen to control rise
time.
Tamper Indication Circuit
The M41T256Y provides an independent input
pin, the Tamper Pin (TP) which can be used to
monitor a signal which can result in the setting of
the Tamper Bit (TB) if the Tamper Enable Bit
(TEB) is set to a '1.'
The Tamper Pin is triggered by being connected to
V
CC
/V
BAT
through an external switch. This switch
is normally open in the application, allowing the pin
to be “floating” (internally latched to V
SS
when TEB
is set). When this switch is closed (connecting the
pin to V
CC
/V
BAT
), the Tamper Bit will be immedi-
ately set. This allows the user to determine if the
device has been physically moved or tampered
with. The Tamper Bit is a “read only” bit and is re-
set only by taking the Tamper Pin to ground and
resetting the Tamper Enable Bit to '0.'
This function operates both under normal power,
and in battery back-up. If the switch closes during
a power-down condition, the bit will still be set cor-
rectly.
Note:
Upon initial battery attach or initial power
application without the battery, the state of TEB
(and TB) will be undetermined. Therefore TEB
must be initialized to a '0.'
Tamper Event Time-Stamp
If a tamper occurs, not only will the Tamper Bit be
set, but the event will also automatically be time-
stamped. This is accomplished by freezing the
normal update of the clock registers (7FF7h
through 7FFFh) immediately following a tamper
event. Thus, when tampering occurs, the user may
first read the time registers to determine exactly
when the tamper event occurred, then re-enable
the clock update to the current time (and reset the
Tamper Bit, TB) by resetting the Tamper Enable
Bit (TEB).
The time update will then resume, and after either
a Stop Condition or incrementing the address
pointer to a RAM address and back, the clock can
be read to determine the current time.
Note:
The Tamper Bit (TB) must always be set to
'0' in order to read the current time.
Calibrating the Clock
The M41T256Y is driven by a quartz controlled os-
cillator with a nominal frequency of 32,768 Hz. The
devices are tested not exceed +/–35 PPM (parts
per million) oscillator frequency error at 25
o
C,
which equates to about +/–1.53 minutes per
month. When the Calibration circuit is properly em-
ployed, accuracy improves to better than +1/–2
PPM at 25°C.
The oscillation rate of crystals changes with tem-
perature (see Figure 16, page 20). Therefore, the
M41T256Y design employs periodic counter cor-
rection. The calibration circuit adds or subtracts
counts from the oscillator divider circuit at the di-
vide by 256 stage, as shown in Figure 17, page 20.
The number of times pulses which are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value load-
ed into the five Calibration bits found in the Control
Register. Adding counts speeds the clock up, sub-
tracting counts slows the clock down.
The Calibration bits occupy the five lower order
bits (D4-D0) in the Control Register (7FF8h).
These bits can be set to represent any value be-
tween 0 and 31 in binary form. Bit D5 is a Sign Bit;
'1' indicates positive calibration, '0' indicates nega-
tive calibration. Calibration occurs within a 64
minute cycle. The first 62 minutes in the cycle
may, once per minute, have one second either
shortened by 128 or lengthened by 256 oscillator
cycles. If a binary '1' is loaded into the register,
only the first 2 minutes in the 64 minute cycle will
be modified; if a binary 6 is loaded, the first 12 will
be affected, and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 PPM of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is running at exactly 32,768 Hz, each
of the 31 increments in the Calibration byte would
represent +10.7 or –5.35 seconds per month
which corresponds to a total range of +5.5 or –2.75
minutes per month.
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