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參數資料
| 型號： | M41T11MHTR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數據恢復及定時提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO28 |
| 封裝： | 0.330 INCH, SNAPHAT, PLASTIC, SOH-28 |
| 文件頁數： | 15/19頁 |
| 文件大?。?/td> | 137K |
| 代理商： | M41T11MHTR |
5/19
M41T11
2-WIRE BUS CHARACTERISTICS
This bus is intended for communication between
different ICs. It consists of two lines: one bi-direc-
tional for data signals (SDA) and one for clock sig-
nals (SCL). Both the SDA and the SCL lines must
be connected to a positive supply voltage via a
pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the bus
is not busy.
– During data transfer, the data line must remain
stable whenever the clock line is High.
– Changes in the data line while the clock line is
High will be interpreted as control signals.
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the High period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and
stop conditions is not limited. The information is
transmitted byte-wide and each receiver acknowl-
edges with a ninth bit.
By definition, a device that gives out a message is
called "transmitter", the receiving device that gets
the message is called "receiver". The device that
controls the message is called "master". The de-
vices that are controlled by the master are called
"slaves".
Table 4. AC Measurement Conditions
Note that Output Hi-Z is defined as the point where data is no longer
driven.
Input Rise and Fall Times
≤ 5ns
Input Pulse Voltages
0.2VCC to 0.8VCC
Input and Output Timing Ref.
Voltages
0.3VCC to 0.7VCC
Figure 4. AC Testing Load Circuit
AI02568
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Table 5. Capacitance (1, 2)
(TA = 25 °C, f = MHz)
Note: 1. Effective capacitance measured with power supply at 5V.
2. Sampled, not 100% tested.
3. Outputs deselected.
Symbol
Parameter
Min
Max
Unit
CIN
Input Capacitance (SCL)
7
pF
COUT
(3)
Output Capacitance (SDA, FT/OUT)
10
pF
tLP
Low-pass filter input time constant (SDA and SCL)
250
1000
ns
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