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M41T0
CLOCK OPERATION
The M41T0 is driven by a quartz controlled oscilla-
tor with a nominal frequency of 32.768kHz. The
accuracy of the Real-Time Clock depends on the
frequency of the quartz crystal that is used as the
time-base for the RTC. The eight-byte Clock Reg-
ister (see Table 8, page 14) is used to both set the
clock and to read the date and time from the clock,
in a binary coded decimal format. Seconds, Min-
utes, and Hours are contained within the first three
registers. Bits D6 and D7 of Clock Register 2
(Hours Register) contain the CENTURY ENABLE
Bit (CEB) and the CENTURY Bit (CB). Setting
CEB to a ’1’ will cause CB to toggle, either from ’0’
to ’1’ or from ’1’ to ’0’ at the turn of the century (de-
pending upon its initial state). If CEB is set to a ’0’,
CB will not toggle. Bits D0 through D2 of Register
3 contain the Day (day of week). Registers 4, 5
and 6 contain the Date (day of month), Month and
Years. The final register is the Control Register. Bit
D7 of Register 0 contains the STOP Bit (ST). Set-
ting this bit to a ’1’ will cause the oscillator to stop.
If the device is expected to spend a significant
amount of time on the shelf, the oscillator may be
stopped to reduce current drain. When reset to a
’0’ the oscillator restarts within four seconds (typi-
cally one second).
The seven clock registers may be read one byte at
a time, or in a sequential block. The Control Reg-
ister (Address location 7) may be accessed inde-
pendently. Provision has been made to assure
that a clock update does not occur while any of the
seven clock addresses are being read. If a clock
address is being read, an update of the clock reg-
isters will be delayed by 250ms to allow the READ
to be completed before the update occurs. This
will prevent a transition of data during the READ.
Note: This 250ms delay affects only the clock reg-
ister update and does not alter the actual clock
time.
Output Driver Pin
The OUT pin is an output driver that reflects the
contents of D7 of the Control Register. In other
words, when D7 of location 7 is a ’0’ then the OUT
pin will be driven low.
Note: The OUT pin is open drain which requires
an external pull-up resistor.
Oscillator Stop Detection
If the Oscillator Fail (OF) Bit is internally set to a ’1,’
this indicates that the oscillator has either stopped,
or was stopped for some period of time and can be
used to judge the validity of the clock and date da-
ta. This bit will be set to ’1’ any time the oscillator
stops. The following conditions can cause the OF
Bit to be set:
– The first time power is applied (defaults to a '1'
on power-up).
– The voltage present on VCC is insufficient to
support oscillation.
– The ST Bit is set to '1.'
– External interference or removal of the crystal.
This bit will remain set to '1' until written to logic '0.'
The oscillator must start and have run for at least
4 seconds before attempting to reset the OF Bit to
'0.' This function operates both under normal pow-
er and in battery back-up.
Initial Power-on Defaults
Upon initial application of power to the device, the
OUT Bit and OF Bit will be set to a '1,' while the ST
Bit will be set to '0.' All other Register bits will ini-
tially power-on in a random state.