參數(shù)資料
型號(hào)： M41T00M6E
廠商： STMICROELECTRONICS
元件分類： 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述： REAL TIME CLOCK, PDSO8
封裝： 0.150 INCH, LEAD FREE, PLASTIC, SOIC-8
文件頁(yè)數(shù)： 2/25頁(yè)
文件大小： 202K
代理商： M41T00M6E
Device operation
M41T00
2.7
Characteristics
2.8
READ mode
In this mode, the master reads the M41T00 slave after setting the slave address (see
Figure 7). Following the WRITE mode control bit (R/W = 0) and the acknowledge bit, the
word address An is written to the on-chip address pointer. Next the START condition and
slave address are repeated, followed by the READ mode control bit (R/W = 1). At this point,
the master transmitter becomes the master receiver. The data byte which was addressed
will be transmitted and the master receiver will send an acknowledge bit to the slave
transmitter. The address pointer is only incremented on reception of an acknowledge bit.
The M41T00 slave transmitter will now place the data byte at address An+1 on the bus. The
master receiver reads and acknowledges the new byte and the address pointer is
incremented to An+2.
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
An alternate READ mode may also be implemented, whereby the master reads the M41T00
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer.
Table 2.
AC characteristics
Symbol
Parameter(1)
1.
Valid for ambient operating temperature: TA = –40 to 85°C; VCC = 2.0 to 5.5 V (except where noted).
Min
Typ
Max
Units
fSCL
SCL clock frequency
0
100
kHz
tLOW
Clock low period
4.7
s
tHIGH
Clock high period
4s
tR
SDA and SCL rise time
1s
tF
SDA and SCL fall time
300
ns
tHD:STA
START condition hold time
(after this period the first clock pulse is generated)
4s
tSU:STA
START condition setup time
(only relevant for a repeated start condition)
4.7
s
tHD:DAT
(2)
2.
Transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling
edge of SCL.
Data hold time
0
ns
tSU:DAT
Data setup time
250
ns
tSU:STO
STOP condition setup time
4.7
s
tBUF
Time the bus must be free before a new
transmission can start
4.7
s
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