- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359061 > M41ST95YMX6E (意法半導(dǎo)體) TWO HEADED HOOD COVER PDF資料下載
參數(shù)資料
| 型號： | M41ST95YMX6E |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | TWO HEADED HOOD COVER |
| 中文描述： | 5.0或3.0V，512位（64位× 8）串行時鐘（SPI）的靜態(tài)存儲器和NVRAM監(jiān) |
| 文件頁數(shù)： | 10/35頁 |
| 文件大?。?/td> | 545K |
| 代理商： | M41ST95YMX6E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁
M41ST95Y*, M41ST95W
10/35
Signal Description
Serial Data Output (SDO).
The output pin is
used to transfer data serially out of the Memory.
Data is shifted out on the falling edge of the serial
clock.
Serial Data Input (SDI).
The input pin is used to
transfer data serially into the device. Instructions,
addresses, and the data to be written, are each re-
ceived this way. Input is latched on the rising edge
of the serial clock.
Serial Clock (SCL).
The serial clock provides the
timing for the serial interface (as shown in
Figure
9., page 11
and
Figure 10., page 11
). The W/R
Bit, addresses, or data are latched, from the input
pin, on the rising edge of the clock input. The out-
put data on the SDO pin changes state after the
falling edge of the clock input.
The M41ST95Y/W can be driven by a microcon-
troller with its SPI peripheral running in either of
the two following modes:
(CPOL, CPHA) = ('0', '0') or
(CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in
by the low-to-high transition of clock SCL, and out-
put data (SDO) is shifted out on the high-to-low
transition of SCL (see Table
2
and Figure
8
).
Chip Enable (E).
When E is high, the memory
device is deselected, and the SDO output pin is
held in its high impedance state.
After power-on, a high-to-low transition on E is re-
quired prior to the start of any operation.
Table 2. Function Table
Note: 1. SDO remains at High Z until eight bits of data are ready to be shifted out during a READ.
Figure 8. Data and Clock Timing
Mode
E
SCL
SDI
SDO
Disable Reset
H
Input Disabled
Input Disabled
High Z
WRITE
L
Data Bit latch
High Z
READ
X
Next data bit shift
(1)
AI04630
AI04631
AI06368
SCL
SCL
MSB
LSB
CPHA
SDI
0
1
CPOL
0
1
MSB
LSB
SDO
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M41ST95YMX6F | TWO HEADED HOOD KIT M/M |
| M41ST95YMX6TR | DB9 2HEAD HOOD KIT MALE - MALE |
| M41ST95YMH6 | MOD CONN, RJ-11, 4 WIRE |
| M41ST95YMH6E | MMJ IN-LINE COUPLER F/F STRAIG |
| M41ST95YMH6F | MMJ IN-LINE COUPLER F/F CROSSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M41ST95YMX6F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
| M41ST95YMX6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
| M41T0 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL REAL-TIME CLOCK |
| M41T0_08 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Serial real-time clock |
| M41T0_11 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Serial real-time clock |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。