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參數(shù)資料
| 型號： | M41ST95YMX6 |
| 廠商： | 意法半導體 |
| 英文描述： | TWO-HEADED HOOD-COVER ONL |
| 中文描述： | 5.0或3.0V，512位（64位× 8）串行時鐘（SPI）的靜態(tài)存儲器和NVRAM監(jiān) |
| 文件頁數(shù)： | 9/35頁 |
| 文件大?。?/td> | 545K |
| 代理商： | M41ST95YMX6 |
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M41ST95Y*, M41ST95W
OPERATION
The M41ST95Y/W clock operates as a slave de-
vice on the SPI serial bus. Each memory device is
accessed by a simple serial interface that is SPI
bus compatible. The bus signals are SCL, SDI and
SDO (see
Table 1., page 5
and
Figure 7., page 8
).
The device is selected when the Chip Enable input
(E) is held low. All instructions, addresses and
data are shifted serially in and out of the chip. The
most significant bit is presented first, with the data
input (SDI) sampled on the first rising edge of the
clock (SCL) after the Chip Enable (E) goes low.
The 64 bytes contained in the device can then be
accessed sequentially in the following order:
1.
Tenths/Hundredths of a Second Register
2.
Seconds Register
3.
Minutes Register
4.
Century/Hours Register
5.
Day Register
6.
Date Register
7.
Month Register
8.
Year Register
9.
Control Register
10. Watchdog Register
11 - 16.Alarm Registers
17 - 19.Reserved
20.
Square Wave Register
21 - 64.User RAM
The M41ST95Y/W clock continually monitors V
CC
for an out-of tolerance condition. Should V
CC
fall
below V
PFD
, the device terminates an access in
progress and resets the device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data from being written
to the device from a an out-of-tolerance system.
When V
CC
falls below V
SO
, the device automati-
cally switches over to the battery and powers
down into an ultra low current mode of operation to
conserve battery life. As system power returns and
V
CC
rises above V
SO
, the battery is disconnected,
and the power supply is switched to external V
CC
.
Write protection continues until V
CC
reaches
V
PFD
(min) plus t
REC
(min). For more information
on Battery Storage Life refer to Application Note
AN1012.
SPI Bus Characteristics
The Serial Peripheral interface (SPI) bus is intend-
ed for synchronous communication between dif-
ferent ICs. It consists of four signal lines: Serial
Data Input (SDI), Serial Data Output (SDO), Serial
Clock (SCL) and a Chip Enable (E).
By definition a device that gives out a message is
called “transmitter,” the receiving device that gets
the message is called “receiver.” The device that
controls the message is called “master.” The de-
vices that are controlled by the master are called
“slaves.”
The E input is used to initiate and terminate a data
transfer. The SCL input is used to synchronize
data transfer between the master (micro) and the
slave (M41ST95Y/W) devices.
The SCL input, which is generated by the micro-
controller, is active only during address and data
transfer to any device on the SPI bus (see
Figure
7., page 8
).
The M41ST95Y/W can be driven by a microcon-
troller with its SPI peripheral running in either of
the two following modes:
(CPOL, CPHA) = ('0', '0') or
(CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in
by the low-to-high transition of clock SCL, and out-
put data (SDO) is shifted out on the high-to-low
transition of SCL (see
Table 2., page 10
and
Fig-
ure 8., page 10
).
There is one clock for each bit transferred. Ad-
dress and data bits are transferred in groups of
eight bits. Due to memory size the second most
significant address bit is a Don’t Care (address bit
6).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M41ST95YMX6E | TWO HEADED HOOD COVER |
| M41ST95YMX6F | TWO HEADED HOOD KIT M/M |
| M41ST95YMX6TR | DB9 2HEAD HOOD KIT MALE - MALE |
| M41ST95YMH6 | MOD CONN, RJ-11, 4 WIRE |
| M41ST95YMH6E | MMJ IN-LINE COUPLER F/F STRAIG |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M41ST95YMX6E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
| M41ST95YMX6F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
| M41ST95YMX6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
| M41T0 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL REAL-TIME CLOCK |
| M41T0_08 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Serial real-time clock |
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