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參數(shù)資料
| 型號： | M41ST95YMH6 |
| 廠商： | 意法半導體 |
| 英文描述： | MOD CONN, RJ-11, 4 WIRE |
| 中文描述： | 5.0或3.0V，512位（64位× 8）串行時鐘（SPI）的靜態(tài)存儲器和NVRAM監(jiān) |
| 文件頁數(shù)： | 14/35頁 |
| 文件大?。?/td> | 545K |
| 代理商： | M41ST95YMH6 |
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M41ST95Y*, M41ST95W
14/35
Figure 13. WRITE Mode Sequence
Data Retention Mode
With valid V
CC
applied, the M41ST95Y/W can be
accessed as described above with READ or
WRITE Cycles. Should the supply voltage decay,
the M41ST95Y/W will automatically deselect,
write protecting itself (and any external SRAM)
when V
CC
falls between V
PFD
(max) and
V
PFD
(min). This is accomplished by internally in-
hibiting access to the clock registers. At this time,
the Reset pin (RST) is driven active and will re-
main active until V
CC
returns to nominal levels. Ex-
ternal RAM access is inhibited in a similar manner
by forcing E
CON
to a high level. This level is within
0.2 volts of the V
BAT
. E
CON
will remain at this level
as long as V
CC
remains at an out-of-tolerance con-
dition. When V
CC
falls below the Battery Back-up
Switchover Voltage (V
SO
), power input is switched
from the V
CC
pin to the SNAPHAT
battery, and
the clock registers and external SRAM are main-
tained from the attached battery supply.
All outputs become high impedance. The V
OUT
pin
is capable of supplying 100 μA of current to the at-
tached memory with less than 0.3 volts drop under
this condition. On power up, when V
CC
returns to
a nominal value, write protection continues for
t
REC
by inhibiting E
CON
. The RST signal also re-
mains active during this time (see
Figure
21., page 28
).
Note:
Most low power SRAMs on the market to-
day can be used with the M41ST95Y/W RTC SU-
PERVISOR. There are, however some criteria
which should be used in making the final choice of
an SRAM to use.
The SRAM must be designed in a way where the
chip enable input disables all other inputs to the
SRAM. This allows inputs to the M41ST95Y/W
and SRAMs to be “Don’t Care” once V
CC
falls be-
low V
PFD
(min). The SRAM should also guarantee
data retention down to V
CC
= 2.0 volts. The chip
enable access time must be sufficient to meet the
system needs with the chip enable output propa-
gation delays included. If the SRAM includes a
second chip enable pin (E2), this pin should be
tied to V
OUT
.
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0 volts. Manufacturers
generally specify a typical condition for room tem-
perature along with a worst case condition (gener-
ally at elevated temperatures). The system level
requirements will determine the choice of which
value to use. The data retention current value of
the SRAMs can then be added to the I
BAT
value of
the M41ST95Y/W to determine the total current re-
quirements for data retention. The available bat-
tery capacity for the SNAPHAT
of your choice
can then be divided by this current to determine
the amount of data retention available (see
20
).
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
SCL
SDI
E
SDO
7
2
HIGH IMPEDANCE
0
DATA BYTE
7 BIT ADDR
W/R BIT
10
15
MSB
MSB
6
6
5
5
4
4
3
3
2
1
1
0
6
5
4
3
2
1
0
7
7
7
8
9
AI04636
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|---|---|
| M41ST95YMH6E | MMJ IN-LINE COUPLER F/F STRAIG |
| M41ST95YMH6F | MMJ IN-LINE COUPLER F/F CROSSP |
| M41ST95YMH6TR | CLUSTER BAR, RJ-11 W/ (8) 6-WI |
| M41T00 | Serial Access TIMEKEEPER |
| M41T00M | Serial Access TIMEKEEPER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M41ST95YMH6E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
| M41ST95YMH6F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
| M41ST95YMH6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
| M41ST95YMX6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
| M41ST95YMX6E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
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