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參數(shù)資料
| 型號： | M41ST95Y |
| 廠商： | 意法半導體 |
| 英文描述： | 5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
| 中文描述： | 5.0或3.0V，512位（64位× 8）串行時鐘（SPI）的靜態(tài)存儲器和NVRAM監(jiān) |
| 文件頁數(shù)： | 13/35頁 |
| 文件大?。?/td> | 545K |
| 代理商： | M41ST95Y |
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M41ST95Y*, M41ST95W
READ and WRITE Cycles
Address and data are shifted MSB first into the Se-
rial Data Input (SDI) and out of the Serial Data
Output (SDO). Any data transfer considers the first
bit to define whether a READ or WRITE will occur.
This is followed by seven bits defining the address
to be read or written. Data is transferred out of the
SDO for a READ operation and into the SDI for a
WRITE operation. The address is always the sec-
ond through the eighth bit written after the Enable
(E) pin goes low. If the first bit is a '1,' one or more
WRITE cycles will occur. If the first bit is a '0,' one
or more READ cycles will occur (see Figure
12
and
Figure 13., page 14
).
Data transfers can occur one byte at a time or in
multiple byte burst mode, during which the ad-
dress pointer will be automatically incremented.
For a single byte transfer, one byte is read or writ-
ten and then E is driven high. For a multiple byte
transfer all that is required is that E continue to re-
main low. Under this condition, the address pointer
will continue to increment as stated previously. In-
crementing will continue until the device is dese-
lected by taking E high. The address will wrap to
00h after incrementing to 3Fh.
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). Although the clock contin-
ues to maintain the correct time, this will prevent
updates of time and date during either a READ or
WRITE of these address locations by the user.
The update will resume either due to a deselect
condition or when the pointer increments to an
non-clock or RAM address (08h to 3Fh).
Note:
This is true both in READ and WRITE mode.
Figure 12. READ Mode Sequence
SCL
SDI
E
SDO
2
HIGH IMPEDANCE
W/R BIT
7 BIT ADDRESS
0
MSB
DATA OUT
(BYTE 1)
MSB
MSB
DATA OUT
(BYTE 2)
1
12 13 14 15 16
17
22
3
4
5
6
7
8
9
2
0
1
3
4
5
6
7
2
0
1
3
4
5
6
7
2
0
1
3
4
5
6
7
AI04635
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M41ST95YMH6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
| M41ST95YMH6E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
| M41ST95YMH6F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
| M41ST95YMH6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
| M41ST95YMX6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
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