參數資料
型號: M41ST87WMX6TR
廠商: 意法半導體
英文描述: 5.0, 3.3, or 3.0V, 1280 bit (160 x8) Secure Serial RTC and NVRAM Supervisor with Tamper Detection
中文描述: 5.0,3.3,或3.0V,1280位(160 × 8)安全串行時鐘和NVRAM篡改檢測與監(jiān)控
文件頁數: 6/40頁
文件大?。?/td> 610K
代理商: M41ST87WMX6TR
M41ST87Y, M41ST87W
6/40
Figure 2. Logic Diagram
Note: 1. Open drain output
2. Programmable output (Open drain or Full-CMOS)
Figure 3. 28-pin, 300mil SOIC (MX)
Connections
Note: No Function (NF) pins should be tied to V
SS
. Pins 1, 2, 3, and
4 are internally shorted together.
Table 1. Signal Names
Note: 1. Open drain output
2. Programmable output (Open drain or Full-CMOS)
3. Should be connected to V
SS
.
AI07023
SCL
VCC
M41ST87Y
M41ST87W
EX
VSS
VBAT
SDA
RSTIN1
IRQ/OUT(1)
SQW/FT(2)
WDI
RSTIN2
TP1IN
PFI2
TP2IN
PFI1
E
CON
RST(1)
PFO1(2)
PFO2(2)
VOUT
F32k(1)
TPCLR
AI07025b
8
9
10
11
12
13
14
2
3
4
5
6
7
22
21
20
19
18
17
16
15
28
27
26
25
24
23
1
RSTIN1
RSTIN2
PFO1
PFI2
VSS
NF
NF
NC
NC
SQW/FT
WDI
IRQ/OUT
VOUT
TP2IN
F32k
TP1IN
RST
EX
PFI1
SCL
TPCLR
SDA
ECON
VBAT
NF
NF
VCC
M41ST87Y
M41ST87W
PFO2
E
CON
Conditioned Chip Enable Output
EX
External Chip Enable
IRQ/OUT
(1)
Interrupt/Out Output
(Open drain)
PFI
1
Power Fail Input 1
PFI
2
Power Fail Input 2
PFO
1(2)
Power Fail Output 1
PFO
2(2)
Power Fail Output 2
RST
(1)
Reset Output (Open Drain)
RSTIN1
Reset 1 Input
RSTIN2
Reset 2 Input
SCL
Serial Clock Input
SDA
Serial Data Input/Output
SQW/FT
(2)
Square Wave Output/Frequency
Test
WDI
Watchdog Input
V
CC
Supply Voltage
V
OUT
Voltage Output
V
SS
Ground
F
32k(1)
32kHz Square Wave Output
(Open drain)
TP1
IN
Tamper Pin 1 Input
TP2
IN
Tamper Pin 2 Input
TP
CLR
Tamper Pin RAM Clear
V
BAT
Positive Battery Pin Input
NF
(3)
No Function
NC
No Connect
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