參數(shù)資料
型號: M41ST85YSH
廠商: 意法半導體
英文描述: Shielded Multiconductor Cable; Number of Conductors:4; Conductor Size AWG:22; No. Strands x Strand Size:19 x 34; Jacket Material:Polyvinylchloride (PVC); Leaded Process Compatible:Yes; Temperature Max:105 C; Voltage Nom.:300V RoHS Compliant: Yes
中文描述: 5.0或3.0V,512位64 × 8串行時鐘和NVRAM督導員
文件頁數(shù): 12/33頁
文件大?。?/td> 464K
代理商: M41ST85YSH
M41ST85Y, M41ST85W
12/33
Figure 11. WRITE Cycle Timing: RTC & External SRAM Control Signals
Figure 12. Bus Timing Requirements Sequence
Table 6. AC Characteristics
Note: 1. Valid for Ambient Operating Temperature: T
A
= –40 to 85°C; V
CC
= 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
Symbol
Parameter
(1)
Min
Max
Unit
f
SCL
SCL Clock Frequency
0
400
kHz
t
BUF
Time the bus must be free before a new transmission can start
1.3
μs
t
EXPD
EX to E
CON
Propagation Delay
M41ST85Y
10
ns
M41ST85W
15
t
F
SDA and SCL Fall Time
300
ns
t
HD:DAT(2)
Data Hold Time
0
μs
t
HD:STA
START Condition Hold Time
(after this period the first clock pulse is generated)
600
ns
t
HIGH
Clock High Period
600
ns
t
LOW
Clock Low Period
1.3
μs
t
R
SDA and SCL Rise Time
300
ns
t
SU:DAT
Data Setup Time
100
ns
t
SU:STA
START Condition Setup Time
(only relevant for a repeated start condition)
600
ns
t
SU:STO
STOP Condition Setup Time
600
ns
AI03663
EX
ECON
tEXPD
tEXPD
AI00589
SDA
P
tSU:STO
tSU:STA
tHD:STA
SR
SCL
tSU:DAT
tF
tHD:DAT
tR
tHIGH
tLOW
tHD:STA
tBUF
S
P
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