參數(shù)資料
型號(hào)： M41ST85Y-85MH6
廠商： STMICROELECTRONICS
元件分類： 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述： 1 TIMER(S), REAL TIME CLOCK, PDSO28
封裝： 0.330 INCH, SNAPHAT, PLASTIC, SOH-28
文件頁(yè)數(shù)： 6/32頁(yè)
文件大?。?/td> 171K
代理商： M41ST85Y-85MH6
M41ST85Y, M41ST85W
14/32
CLOCK OPERATION
The eight byte clock register (see Table 3, page
15) is used to both set the clock and to read the
date and time from the clock, in a binary coded
decimal format. Tenths/Hundredths of Seconds,
Seconds, Minutes, and Hours are contained within
the first four registers. Bits D6 and D7 of clock reg-
ister 3 (Century/Hours Register) contain the CEN-
TURY ENABLE Bit (CEB) and the CENTURY Bit
(CB). Setting CEB to a ‘1’ will cause CB to toggle,
either from ‘0’ to ‘1’ or from ‘1’ to ‘0’ at the turn of
the century (depending upon its initial state). If
CEB is set to a ‘0’, CB will not toggle. Bits D0
through D2 of register 4 contain the Day (day of
week). Registers 5, 6 and 7 contain the Date (day
of month), Month and Years. The ninth clock reg-
ister is the Control Register (this is described in the
Clock Calibration section). Bit D7 of register 1 con-
tains the STOP Bit (ST). Setting this bit to a ‘1’ will
cause the oscillator to stop. If the device is
expected to spend a significant amount of time on
the shelf, the oscillator may be stopped to reduce
current drain. When reset to a ‘0’ the oscillator
restarts within one second.
The eight Clock Registers may be read one byte at
a time, or in a sequential block. The Control Reg-
ister (Address location 08h) may be accessed
independently. Provision has been made to
assure that a clock update does not occur while
any of the seven clock addresses are being read.
If a clock address is being read, an update of the
clock registers will be halted. This will prevent a
transition of data during the read.
Note: Upon power-up following a power failure,
the HT bit will automatically be set to a ‘1’. This will
prevent the clock from updating the TIMEKEEPER
registers, and will allow the user to read the exact
time of the power-down event. Resetting the HT bit
to a ‘0’ will allow the clock to update the TIME-
KEEPER registers with the current time.
Data Retention Mode
With valid VCC applied, the M41ST85Y/W can be
accessed as described above with read or write
cycles. Should the supply voltage decay, the
M41ST85Y/W will automatically deselect, write
protecting itself (and any external SRAM) when
VCC falls between VPFD (max) and VPFD (min).
This is accomplished by internally inhibiting
access to the clock registers. At this time, the
Reset pin (RST) is driven active and will remain
active until VCC returns to nominal levels. External
RAM access is inhibited in a similar manner by
forcing ECON to a high level. This level is within 0.2
volts of the VBAT.ECON will remain at this level as
long as VCC remains at an out-of tolerance condi-
tion. When VCC falls below the Battery Back-up
Switchover Voltage (VSO), power input is switched
from the VCC pin to the SNAPHAT battery and the
clock registers and external SRAM are maintained
from the attached battery supply.
All outputs become high impedance. The VOUT pin
is capable of supplying 100
A of current to the
attached memory with less than 0.3 volts drop
under this condition. On power up, when VCC
returns to a nominal value, write protection contin-
ues for tREC by inhibiting ECON. The RST signal
also remains active during this time (see Figure
21, page 26).
Note: Most low power SRAMs on the market
today can be used with the M41ST85Y/W RTC
SUPERVISOR. There are, however some criteria
which should be used in making the final choice of
an SRAM to use. The SRAM must be designed in
a way where the chip enable input disables all
other inputs to the SRAM. This allows inputs to the
M41ST85Y/W and SRAMs to be Don’t Care once
VCC falls below VPFD(min). The SRAM should also
guarantee data retention down to VCC=2.0 volts.
The chip enable access time must be sufficient to
meet the system needs with the chip enable output
propagation delays included. If the SRAM includes
a second chip enable pin (E2), this pin should be
tied to VOUT.
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0 volts. Manufacturers
generally specify a typical condition for room tem-
perature along with a worst case condition (gener-
ally at elevated temperatures). The system level
requirements will determine the choice of which
value to use. The data retention current value of
the SRAMs can then be added to the IBAT value of
the M41ST85Y/W to determine the total current
requirements for data retention. The available bat-
tery capacity for the SNAPHAT of your choice can
then be divided by this current to determine the
amount of data retention available (see Table 18,
page 30).
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
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