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參數(shù)資料
| 型號： | M41ST84Y-70MH6TR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO28 |
| 封裝： | 0.330 INCH, SNAPHAT, PLASTIC, SOH-28 |
| 文件頁數(shù)： | 2/32頁 |
| 文件大?。?/td> | 168K |
| 代理商： | M41ST84Y-70MH6TR |
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M41ST84Y, M41ST84W
10/32
Figure 9. Bus Timing Requirements Sequence
Table 2. AC Characteristics
Note: 1. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
Symbol
Parameter
Min
Max
Unit
fSCL
SCL Clock Frequency
0
400
kHz
tBUF
Time the bus must be free before a new transmission can start
1.3
s
tF
SDA and SCL Fall Time
300
ns
tHD:DAT
Data Hold Time
0
s
tHD:STA
START Condition Hold Time
(after this period the first clock pulse is generated)
600
ns
tHIGH
Clock High Period
600
ns
tLOW
Clock Low Period
1.3
s
tR
SDA and SCL Rise Time
300
ns
tSU:DAT
(1)
Data Setup Time
100
ns
tSU:STA
START Condition Setup Time
(only relevant for a repeated start condition)
600
ns
tSU:STO
STOP Condition Setup Time
600
ns
AI00589
SDA
P
tSU:STO
tSU:STA
tHD:STA
SR
SCL
tSU:DAT
tF
tHD:DAT
tR
tHIGH
tLOW
tHD:STA
tBUF
S
P
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