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參數(shù)資料
| 型號(hào)： | M40Z111SH |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | NVRAM CONTROLLER for up to TWO LPSRAM |
| 中文描述： | NVRAM中控制器長(zhǎng)達(dá)2 LPSRAM |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 89K |
| 代理商： | M40Z111SH |
Manufacturers generally specify a typical condition
for room temperature along with a worst case
condition (generally at elevated temperatures). The
system level requirements will determine the
choice of which value to use. The data retention
current value of the SRAMs can then be added to
the I
CCDR
value of the M40Z111/111W to determine
the total current requirements for data retention.
The available battery capacity for the SNAPHAT of
your choice can then be divided by this current to
determine the amount of data retention available
(see Table 7). For more information on Battery
Storage Life refer to the Application Note AN1012.
V
CC
NOISE AND NEGATIVE-GOING TRAN-
SIENTS
I
CC
transients, including those produced by output
switching, can produce voltage fluctuations, result-
ing in spikes on the V
CC
bus. These transients can
be reduced if capacitors are used to store energy,
which stabilizes the V
CC
bus. The energy stored in
the bypass capacitors will be released as low going
spikes are generated or energy will be absorbed
when overshoots occur.
Input Rise and Fall Times
≤
5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Table 3. AC Measurement Condition
AI02326
CL = 100pF
or 5pF
CL includes JIG capacitance
645
DEVICE
UNDER
TEST
1.75V
Figure 4. AC Testing Load Circuit
Symbol
Parameter
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
8
pF
C
OUT
(2)
Output Capacitance
V
OUT
= 0V
10
pF
Note:
1. Sampled only, not 100% tested.
2. Outputs deselected.
Table 4. Capacitance
(1)
(T
A
= 25
°
C; f = 1MHz)
A ceramic bypass capacitor value of 0.1
μ
F (as
shown in Figure 4) is recommended in order to
provide the needed filtering. In addition to tran-
sients that are caused by normal SRAM operation,
power cycling can generate negative voltage
spikes on V
CC
that drive it to values below V
SS
by
as much as one volt. These negative spikes can
cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage
spikes, ST recommends connecting a schottky di-
ode from V
CC
to V
SS
(cathode connected to V
CC
,
anode to V
SS
).
4/12
M40Z111, M40Z111W
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M40Z111W | 1501A CMP 4P24 GY 1000F SP |
| M40Z111WMH | NVRAM CONTROLLER for up to TWO LPSRAM |
| M40Z111WSH | NVRAM CONTROLLER for up to TWO LPSRAM |
| M40Z111MH | Multiconductor Cable; Number of Conductors:8; No. Strands x Strand Size:Solid; Jacket Material:Polyvinylchloride (PVC); Number of Pairs:4; Leaded Process Compatible:Yes |
| M40Z300 | NVRAM CONTROLLER for up to EIGHT LPSRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M40Z111W | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V or 3V NVRAM supervisor for up to two LPSRAMs |
| M40Z111WMH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:NVRAM CONTROLLER for up to TWO LPSRAM |
| M40Z111WMH6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V OR 3V NVRAM SUPERVISOR FOR UP TO TWO LPSRAMs |
| M40Z111WMH6E | 功能描述:監(jiān)控電路 N-Ch, 5V or 3V NVRAM up to 2 LPSRAMs RoHS:否 制造商:STMicroelectronics 監(jiān)測(cè)電壓數(shù): 監(jiān)測(cè)電壓: 欠電壓閾值: 過(guò)電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| M40Z111WMH6F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V or 3V NVRAM supervisor for up to two LPSRAMs |
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