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參數(shù)資料
| 型號(hào)： | M40Z111 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | NVRAM Controller for up to Two LPSRAM(NVRAM控制器) |
| 中文描述： | NVRAM中控制器最多兩個(gè)LPSRAM（NVRAM中控制器） |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 80K |
| 代理商： | M40Z111 |
When V
CC
degradesduring a power failure,E
CON
isforcedinactiveindependentofE.In thissituation,
theSRAM isunconditionallywriteprotectedasV
CC
falls below an out-of-tolerance threshold (V
PFD
).
ThepowerfaildetectionvalueassociatedwithV
PFD
isselectedby theTHS pinand isshownin Table5.
(Note:THS pin mustbe connectedtoeitherV
SS
or
V
OUT
). If chip enable access is in progress during
apowerfaildetection,thatmemorycyclecontinues
tocompletionbeforethememoryiswriteprotected.
If the memory cycle is not terminated within time
t
WP
, E
CON
is unconditionallydriven high, writepro-
tecting the SRAM.
A power failure during a write cycle may corrupt
data at the currently addressed location, but does
not jeopardizethe rest of the SRAM’s contents.At
voltagesbelowV
PFD
(min),theusercanbeassured
the memory will be write protected provided the
V
CC
fall time exceedst
F
.
As V
CC
continues to degrade, the internal switch
disconnectsV
CC
andconnectsthe internalbattery
to V
OUT
. This occurs at the switchover voltage
(V
SO
). Below the V
SO
, the battery provides a volt-
age V
OHB
to the SRAM and can supply current
I
OUT2
(see Table 5). When V
CC
rises above V
SO
,
V
OUT
isswitchedbacktothesupplyvoltage.Output
E
CON
is held inactive for t
ER
(200ms maximum)
after the power supply has reached V
PFD
, inde-
pendent of the E input, to allow for processor
stabilization (seeFigure 6).
DATA RETENTION LIFETIME CALCULATION
Most low power SRAMs on the market today can
be used with the M40Z111/111WNVRAMControl-
ler. Thereare, howeversomecriteriawhichshould
be used in making the final choiceof whichSRAM
to use. The SRAM must be designed in a way
where the chip enable input disables all other in-
puts to the SRAM. This allows inputs to the
M40Z111/111Wand SRAMsto beDon’tCareonce
V
CC
fallsbelow V
PFD
(min).TheSRAMshouldalso
guarantee data retention down to V
CC
=2.0V.The
chipenableaccesstimemust be sufficientto meet
thesystemneedswiththechipenablepropagation
delaysincluded.Ifdataretentionlifetimeis acritical
parameterfor the system, it is importantto review
the data retention current specifications for the
particular SRAMs being evaluated. Most SRAMs
specifya data retentioncurrent at 3.0V.
Manufacturersgenerallyspecifya typicalcondition
for room temperature along with a worst case
condition(generallyat elevatedtemperatures).The
system level requirements will determine the
choice of which value to use. The data retention
current value of the SRAMs can then be added to
theI
CCDR
valueof theM40Z111/111Wto determine
the total current requirementsfor data retention.
Theavailablebatterycapacityforthe SNAPHATof
your choice can then be divided by this current to
determine the amount of data retention available
(see Table 7). For more information on Battery
StorageLife refer to the ApplicationNote AN1012.
AI02394
VCC
E
ECON
VSS
VOUT
VCC
CMOS
SRAM
x8 or x16
3.3V or 5V
THS
E
0.1
μ
F
0.1
μ
F
M40Z111
Thereshold
1N5817
or
MBR5120T3
Figure 3. HardwareHookup
3/12
M40Z111, M40Z111W
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| M40Z300AV | 3V NVRAM Supervisor for Up to 8 LPSRAMs |
| M40Z300AVMH1E | 3V NVRAM Supervisor for Up to 8 LPSRAMs |
| M40Z300AVMH1F | 3V NVRAM Supervisor for Up to 8 LPSRAMs |
| M40Z300AVMH6E | 3V NVRAM Supervisor for Up to 8 LPSRAMs |
| M40Z300AVMH6F | 3V NVRAM Supervisor for Up to 8 LPSRAMs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M40Z111_07 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V or 3V NVRAM supervisor for up to two LPSRAMs |
| M40Z111MH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:NVRAM CONTROLLER for up to TWO LPSRAM |
| M40Z111MH6 | 功能描述:監(jiān)控電路 Dual Low Power SRAM RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| M40Z111MH6E | 功能描述:監(jiān)控電路 Dual Low Power SRAM RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| M40Z111MH6F | 功能描述:監(jiān)控電路 Dual Low Power SRAM RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復(fù)位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復(fù)位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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