參數(shù)資料
型號(hào): M4-64/32-15JC
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: High Performance E 2 CMOS In-System Programmable Logic
中文描述: EE PLD, 15 ns, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 3/46頁
文件大?。?/td> 754K
代理商: M4-64/32-15JC
MACH 4 Family
11
The ip-op can be congured as a D-type or T-type latch. J-K or S-R registers can be
synthesized. The primary ip-op congurations are shown in Figure 6, although others are
possible. Flip-op functionality is dened in Table 8. Note that a J-K latch is inadvisable as it will
cause oscillation if both J and K inputs are HIGH.
DQ
AP AR
DQ
AP AR
LQ
AP AR
LQ
AP AR
G
TQ
AP AR
17466G-011
Figure 6. Primary Macrocell Congurations
g. Combinatorial with programmable polarity
a. D-type with XOR
b. D-type with programmable D polarity
c. Latch with XOR
d. Latch with programmable D polarity
e. T-type with programmable T polarity
f. Combinatorial with XOR
相關(guān)PDF資料
PDF描述
M4-64/32-15VC High Performance E 2 CMOS In-System Programmable Logic
M4LV-128/64-12VC High Performance E 2 CMOS In-System Programmable Logic
M4LV-128/64-12VI High Performance E 2 CMOS In-System Programmable Logic
M4LV-128/64-12YC High Performance E 2 CMOS In-System Programmable Logic
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