參數(shù)資料
型號： M4-32/32-7VC48
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： High Performance E 2 CMOS In-System Programmable Logic
中文描述： EE PLD, 7.5 ns, PQFP48
封裝： TQFP-48
文件頁數(shù)： 29/46頁
文件大小： 754K
代理商： M4-32/32-7VC48
MACH 4 Family
35
ICC vs. FREQUENCY
These curves represent the typical power consumption for a particular device at system frequen-
cy. The selected “typical” pattern is a 16-bit up-down counter. This pattern lls the device and
exercises every macrocell. Maximum frequency shown uses internal feedback and a D-type reg-
ister. Power/Speed are optimized to obtain the highest counter frequency and the lowest power.
The highest frequency (LSBs) is placed in common PAL blocks, which are set to high power. The
lowest frequency signals (MSBs) are placed in a common PAL block and set to lowest power.
350
300
250
200
150
100
50
0
10
20
30
40
50
60
70
80
90
100
110
120
130
VCC = 5 V or 3.3 V, TA = 25 C
I CC
(mA)
Frequency (MHz)
17466G-066
M4(LV)-32/32
M4(LV)-64/32
M4(LV)-96/48
M4(LV)-128/64
M4(LV)-192/96
M4(LV)-256/128
Figure 18. MACH 4 ICC Curves at High Speed Mode
350
300
250
200
150
100
50
0
10
20
30
40
50
60
70
80
90
100
110
120
VCC = 5 V or 3.3 V, TA = 25 C
M4(LV)-32/32
I CC
(mA)
Frequency (MHz)
17466G-065
M4(LV)-64/32
M4(LV)-96/48
M4(LV)-128/64
M4(LV)-192/96
M4(LV)-256/128
Figure 19. MACH 4 ICC Curves at Low Power Mode
相關(guān)PDF資料
PDF描述
M4-64/32-12JC High Performance E 2 CMOS In-System Programmable Logic
M4-64/32-12JI High Performance E 2 CMOS In-System Programmable Logic
M4-64/32-12VC High Performance E 2 CMOS In-System Programmable Logic
M4-64/32-12VC48 High Performance E 2 CMOS In-System Programmable Logic
M4-64/32-12VI High Performance E 2 CMOS In-System Programmable Logic
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