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參數資料
| 型號： | M4-192/96-12VI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | High Performance E 2 CMOS In-System Programmable Logic |
| 中文描述： | EE PLD, 12 ns, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數： | 42/46頁 |
| 文件大?。?/td> | 754K |
| 代理商： | M4-192/96-12VI |
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MACH 4 Family
5
FUNCTIONAL DESCRIPTION
The fundamental architecture of MACH 4 devices (Figure 1) consists of multiple, optimized PAL
blocks interconnected by a central switch matrix. The central switch matrix allows
communication between PAL blocks and routes inputs to the PAL blocks. Together, the PAL
blocks and central switch matrix allow the logic designer to create large designs in a single
device instead of having to use multiple devices.
The key to being able to make effective use of these devices lies in the interconnect schemes.
In MACH 4 architecture, the macrocells are exibly coupled to the product terms through the
logic allocator, and the I/O pins are exibly coupled to the macrocells due to the output switch
matrix. In addition, more input routing options are provided by the input switch matrix. These
resources provide the exibility needed to t designs efciently.
Notes:
1. 16 for MACH 4 devices with 1:1 macrocell-I/O cell ratio (see next page).
2. Block clocks do not go to I/O cells in M4(LV)-32/32.
3. M4(LV)-192/96 and M4(LV)-256/128 have dedicated clock pins which cannot be used as inputs and do not connect to the central
switch matrix.
I/O
Pins
Clock/Input
Pins
Central
Switch
Matrix
I/O
Pins
I/O
Pins
Dedicated
Input Pins
PAL Block
Logic
Allocator
with XOR
Output/
Buried
Macrocells
33/
34/
36
16
Clock
Generator
Logic
Array
Output
Switch
Matrix
Input
Switch
Matrix
I/O
Cells
16
8
Note 1
Note 2
Note 3
4
PAL Block
17466G-001
Figure 1. MACH 4 Block Diagram and PAL Block Structure
相關PDF資料 |
PDF描述 |
|---|---|
| M4-32/32-12VI48 | High Performance E 2 CMOS In-System Programmable Logic |
| M4-32/32-15JC | High Performance E 2 CMOS In-System Programmable Logic |
| M4-32/32-15VC | High Performance E 2 CMOS In-System Programmable Logic |
| M4-32/32-15VC48 | High Performance E 2 CMOS In-System Programmable Logic |
| M4-32/32-18JI | High Performance E 2 CMOS In-System Programmable Logic |
相關代理商/技術參數 |
參數描述 |
|---|---|
| M41AH | 制造商:Texas Instruments 功能描述: |
| M41G | 制造商:Altech Corporation 功能描述: |
| M41L091M | 功能描述:JOYSTICK MINI 3AXIS W/BUTTON RoHS:是 類別:電位計，可變電阻器 >> 搖桿 系列:M 標準包裝:200 系列:253 電阻（歐姆）:20k 功率（瓦特）:0.01W 容差:±30% 調節(jié)型:頂部調節(jié) 回轉角度:60° 安裝類型:通孔 封裝/外殼:方形 - 0.768" L x 0.693" W x 0.236" H（19.50mm x 17.60mm x 6.00mm） 包裝:散裝 |
| M41L091P | 制造商:CH Products 功能描述:RESISTIVE MINIATURE JOYSTICK 3 AXES |
| M41L0N1M | 制造商:APEM 功能描述:Joystick, Three Axis, One Pushbutton Potentiometer, Rail to Tail Potentiometer 制造商:APEM 功能描述:JOYSTICK, 1 PB POT RAIL-RAIL POT |
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