參數(shù)資料
型號: M4-128N/64-12JC
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: High Performance E 2 CMOS In-System Programmable Logic
中文描述: EE PLD, 12 ns, PQCC84
封裝: PLASTIC, LCC-84
文件頁數(shù): 9/46頁
文件大小: 754K
代理商: M4-128N/64-12JC
MACH 4 Family
17
PAL Block Clock Generation
Each MACH 4 device has four clock pins that can also be used as inputs. These pins drive a
clock generator in each PAL block (Figure 14). The clock generator provides four clock signals
that can be used anywhere in the PAL block. These four PAL block clock signals can consist of
a large number of combinations of the true and complement edges of the global clock signals.
Table 12 lists the possible combinations.
Note:
1. M4(LV)-32/32 and M4(LV)-64/32 have only two clock pins, GCLK0 and GCLK1. GCLK2 is tied to GCLK0, and GCLK3 is tied to
GCLK1.
To
Central
Switch
Matrix
From
Macrocell
2
From Input Cell
Direct
From
Macrocell
1
Registered/Latched
17466G-002
17466G-003
Figure 12. MACH 4 with 2:1 Macrocell-I/O Cell Ratio
- Input Switch Matrix
Figure 13. MACH 4 with 1:1 Macrocell-I/O Cell Ratio
- Input Switch Matrix
To
Central
Switch
Matrix
From
Macrocell
From
I/O
Pin
GCLK0
GCLK1
GCLK2
GCLK3
Block CLK0
(GCLK0 or GCLK1)
Block CLK1
(GCLK1 or GCLK0)
Block CLK2
(GCLK2 or GCLK3)
Block CLK3
(GCLK3 or GCLK2)
17466G-004
Figure 14. PAL Block Clock Generator 1
相關(guān)PDF資料
PDF描述
M4-128N/64-12JI High Performance E 2 CMOS In-System Programmable Logic
M4-128N/64-15JC High Performance E 2 CMOS In-System Programmable Logic
M4-128N/64-18JI High Performance E 2 CMOS In-System Programmable Logic
M4-128N/64-7JC High Performance E 2 CMOS In-System Programmable Logic
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