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參數(shù)資料
| 型號： | M393T3253FG |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR2 Registered SDRAM MODULE 240pin Registered Module based on 256Mb F-die 72-bit ECC |
| 中文描述： | 注冊的DDR2 SDRAM內存模塊240針腳注冊模塊，基于256Mb的F -死72位ECC |
| 文件頁數(shù)： | 18/18頁 |
| 文件大小： | 387K |
| 代理商： | M393T3253FG |
Rev. 1.3 Aug. 2005
256MB, 512MB Registered DIMMs
DDR2 SDRAM
Operating Temperature Condition
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to
JESD51.2 standard.
2. At 0 - 85
°C, operation temperature range are the temperature which all DRAM specification will be supported.
3. At 85 - 95
°C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to
self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
Input DC Logic Level
Input AC Logic Level
AC Input Test Conditions
Notes:
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC)
max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative
transitions.
Symbol
Parameter
Rating
Units
Notes
TOPER
Operating Temperature
0 to 95
°C
1, 2, 3
Symbol
Parameter
Min.
Max.
Units
Notes
VIH(DC)
DC input logic high
VREF + 0.125
VDDQ + 0.3
V
VIL(DC)
DC input logic low
- 0.3
VREF - 0.125
V
Symbol
Parameter
DDR2-400, DDR2-533
DDR2-667
Units
Notes
Min.
Max.
Min.
Max.
VIH(AC)
AC input logic high
VREF + 0.250
-
VREF + 0.200
V
VIL(AC)
AC input logic low
-
VREF - 0.250
VREF - 0.200
V
Symbol
Condition
Value
Units
Notes
VREF
Input reference voltage
0.5 * VDDQ
V1
VSWING(MAX)
Input signal maximum peak to peak swing
1.0
V
1
SLEW
Input signal minimum slew rate
1.0
V/ns
2, 3
VDDQ
VIH(AC) min
VIH(DC) min
VREF
VIL(DC) max
VIL(AC) max
VSS
< AC Input Test Signal Waveform >
VSWING(MAX)
delta TR
delta TF
VREF - VIL(AC) max
delta TF
Falling Slew =
Rising Slew =
VIH(AC) min - VREF
delta TR
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相關代理商/技術參數(shù) |
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|---|---|
| M393T3253FG0-CC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 256Mb F-die 72-bit ECC |
| M393T3253FG0-CD5/CC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 256Mb F-die 72-bit ECC |
| M393T3253FG3-CC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 256Mb F-die 72-bit ECC |
| M393T3253FG3-CD5/CC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 256Mb F-die 72-bit ECC |
| M393T3253FZ0-CC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 256Mb F-die 72-bit ECC |
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