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參數(shù)資料
| 型號： | M393T3253FG3-CC |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR2 Registered SDRAM MODULE 240pin Registered Module based on 256Mb F-die 72-bit ECC |
| 中文描述： | 注冊的DDR2 SDRAM內(nèi)存模塊240針腳注冊模塊，基于256Mb的F -死72位ECC |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 387K |
| 代理商： | M393T3253FG3-CC |
Rev. 1.3 Aug. 2005
256MB, 512MB Registered DIMMs
DDR2 SDRAM
Parameter
Symbol
DDR2-667
DDR2-533
DDR2-400
Units Notes
min
max
min
max
min
max
DQS input low pulse width
tDQSL
0.35
x
0.35
x
0.35
x
tCK
DQS falling edge to CK setup time
tDSS
0.2
x
0.2
x
0.2
x
tCK
DQS falling edge hold time from CK
tDSH
0.2
x
0.2
x
0.2
x
tCK
Mode register set command cycle time
tMRD
2
x
2
x
2
x
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write preamble
tWPRE
0.35
x
0.35
x
0.35
x
tCK
Address and control input hold time
tIH
275
x375
x
475
x
ps
Address and control input setup time
tIS
200
x250
x
350
x
ps
Read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Active to active command period for 1KB page
size products
tRRD
7.5
x7.5
x
7.5
x
ns
Active to active command period for 2KB page
size products
tRRD
10
x10
x
10
x
ns
Four Activate Window for 1KB page size
products
tFAW
37.5
ns
Four Activate Window for 2KB page size
products
tFAW
50
ns
CAS to CAS command delay
tCCD
2
tCK
Write recovery time
tWR
15
x15
x
15
x
ns
Auto precharge write recovery + precharge time tDAL
tWR+tRP
x
tWR+tRP
x
tWR+tRP
x
tCK
Internal write to read command delay
tWTR
7.5
x7.5
x10
x
ns
Internal read to precharge command delay
tRTP
7.5
ns
Exit self refresh to a non-read command
tXSNR
tRFC + 10
ns
Exit self refresh to a read command
tXSRD
200
tCK
Exit precharge power down to any non-read
command
tXP
2
x
2
x
2
x
tCK
Exit active power down to read command
tXARD
2
x
2
x
2
x
tCK
Exit active power down to read command
(Slow exit, Lower power)
tXARDS
6 - AL
tCK
CKE minimum pulse width
(high and low pulse width)
tCKE
3
33
tCK
ODT turn-on delay
tAOND
22
2222
tCK
ODT turn-on
tAON
tAC(min)
tAC(max)+0.7
tAC(min)
tAC(max)+1
tAC(min)
tAC(max)+1
ns
ODT turn-on(Power-Down mode)
tAONPD
tAC(min)+2
2tCK+tAC(ma
x)+1
tAC(min)+2
2tCK+tAC(ma
x)+1
tAC(min)+2
2tCK+tAC
(max)+1
ns
ODT turn-off delay
tAOFD
2.5
tCK
ODT turn-off
tAOF
tAC(min)
tAC(max)+
0.6
tAC(min)
tAC(max)+ 0.6
tAC(min)
tAC(max)+ 0.6
ns
ODT turn-off (Power-Down mode)
tAOFPD
tAC(min)+2
2.5tCK+tAC(
max)+1
tAC(min)+2
2.5tCK+
tAC(max)+1
tAC(min)+2
2.5tCK+
tAC(max)+1
ns
ODT to power down entry latency
tANPD
3
tCK
ODT power down exit latency
tAXPD
8
tCK
OCD drive mode output delay
tOIT
0
12
0
12
0
12
ns
Minimum time clocks remains ON after CKE
asynchronously drops LOW
tDelay
tIS+tCK +tIH
ns
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M393T3253FG3-CD5/CC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 256Mb F-die 72-bit ECC |
| M393T3253FZ0-CC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 256Mb F-die 72-bit ECC |
| M393T3253FZ0-CD5/CC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 256Mb F-die 72-bit ECC |
| M393T3253FZ3-CC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 256Mb F-die 72-bit ECC |
| M393T3253FZ3-CD5/CC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Registered SDRAM MODULE 240pin Registered Module based on 256Mb F-die 72-bit ECC |
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