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參數(shù)資料
| 型號(hào)： | M390S6450CT1-C7A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 64Mx72 SDRAM DIMM with PLL & Register based on 64Mx4, 4Banks, 8K Ref., 3.3V Synchronous DRAMs with SPD |
| 中文描述： | 64Mx72 SDRAM的內(nèi)存與鎖相環(huán) |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大小： | 220K |
| 代理商： | M390S6450CT1-C7A |
M390S6450CT1
PC133 Registered DIMM
Rev. 0.2 Sept. 2001
td, tr = Delay of register (74ALVCF162835)
Notes :
1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal
because of the buffering in register (74ALVCF162835). Therefore, Input/Output signals of read/write function should be
issued 1CLK earlier as compared to Unbuffered DIMMs.
2. D
IN
is to be issued 1clock after write command in external timing because D
IN
is issued directly to module.
: Don
′
t
care
STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)
REG
Control Signal(RAS,CAS,WE)
*1
*2
*3
D
OUT
*1. Register Input
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLK
RAS
CAS
WE
RAS
CAS
WE
tSAC
tRDL
Read
Command
Row Active
Row Active
Write
Command
Precharge
Command
1CLK
td
tr
td
tr
*2. Register Output
*3. SDRAM
tRAC(refer to *1)
CAS latency(refer to *1)
=2CLK+1CLK
DQ
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
Precharge
Command
CAS latency(refer to *2)
=2CLK
tRAC(refer to *2)
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|---|---|
| M390S6450CT1-C7C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Mx72 SDRAM DIMM with PLL & Register based on 64Mx4, 4Banks, 8K Ref., 3.3V Synchronous DRAMs with SPD |
| M390S6450ET1-C7A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:168pin Registered Module based on 256Mb E-die with 72-bit ECC |
| M390S6450ET1-C7A00 | 制造商:Samsung 功能描述:256 SDRAM MODULE X72 TSOP2-400 - Trays |
| M390S6450ETU-C7A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:168pin Registered Module based on 256Mb E-die with 72-bit ECC |
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