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38K2 Group User’s Manual
List of figures
Fig. 3.5.75 Index00[high]; Structure of External I/O configuration register ........................ 3-78
Fig. 3.5.76 Index03[high]; Structure of Memory address counter ......................................... 3-79
Fig. 3.5.77 Index04[high]; Structure of End address register ................................................ 3-79
Fig. 3.5.78 Structure of A-D control register ............................................................................ 3-79
Fig. 3.5.79 Structure of A-D conversion register 1 ................................................................. 3-80
Fig. 3.5.80 Structure of A-D conversion register 2 ................................................................. 3-80
Fig. 3.5.81 Structure of Watchdog timer control register ....................................................... 3-81
Fig. 3.5.82 Structure of CPU mode register ............................................................................ 3-81
Fig. 3.5.83 Structure of Interrupt request register 1 ............................................................... 3-82
Fig. 3.5.84 Structure of Interrupt request register 2 ............................................................... 3-82
Fig. 3.5.85 Structure of Interrupt control register 1 ................................................................ 3-83
Fig. 3.5.86 Structure of Interrupt control register 2 ................................................................ 3-83
Fig. 3.5.87 Structure of Serial I/O control register .................................................................. 3-84
Fig. 3.5.88 Structure of UART control register ........................................................................ 3-84
Fig. 3.5.89 Structure of Baud rate generator ........................................................................... 3-85
Fig. 3.5.90 Structure of EP01 MAX. packet size register ...................................................... 3-85
Fig. 3.5.91 Structure of EP02 MAX. packet size register ...................................................... 3-85
Fig. 3.5.92 Structure of EP03 MAX. packet size register ...................................................... 3-86
Fig. 3.5.93 Structure of EP00 buffer area set register ........................................................... 3-86
Fig. 3.5.94 Structure of EP01 buffer area set register ........................................................... 3-86
Fig. 3.5.95 Structure of EP02 buffer area set register ........................................................... 3-87
Fig. 3.5.96 Structure of EP03 buffer area set register ........................................................... 3-87
Fig. 3.5.97 Structure of EP10 buffer area set register ........................................................... 3-87
Fig. 3.5.98 Structure of EP11 buffer area set register ........................................................... 3-88
Fig. 3.5.99 Structure of Port P0 pull-up control register ........................................................ 3-88
Fig. 3.5.100 Structure of Port P5 pull-up control register ...................................................... 3-89
Fig. 3.5.101 Structure of Interrupt edge selection register .................................................... 3-89
Fig. 3.5.102 Structure of PLL control register ......................................................................... 3-90
Fig. 3.5.103 Structure of Downstream port control register ................................................... 3-90
Fig. 3.5.104 Structure of MISRG ............................................................................................... 3-91
Fig. 3.5.105 Structure of Flash memory control register ........................................................ 3-91