參數(shù)資料
型號: M38K29F8LHP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封裝: 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù): 106/151頁
文件大小: 1403K
代理商: M38K29F8LHP
38K2 Group
Rev.3.00
Oct 15, 2006
page 58 of 147
REJ03B0193-0300
HUB Function Control Circuit Block Diagram
The HUB function control circuit, as show in the diagram below,
consists of the following blocks.
(1) HUB repeater block
(2) Down-port control block
(3) CPU interface block (CIF)
(1) HUB repeater block
The HUB repeater block, consisting of the circuits listed below,
processes the HUB repeater function sequence. The HUB re-
peater is ready for operation after enabling the USB module
(USBE = “1”).
Repeater circuit (detects SOP/EOP signal)
Frame-time circuit (synchronizes to SOF signal and manages
frames in 1 ms)
Receiver circuit (manages up-port states)
Transmitter circuit (controls up-port outputs)
(2) Down-port control block
The down-port control block, consisting of the circuits listed below,
performs down-port controls under supervision of the HUB re-
peater state operation.
Down-port sequencer circuit
Down-port state change detect circuit
CPU
CIF
HUB Function Control Circuit
USB
transceiver
D0+
D0-
USB down-port 1
transceiver
HUB repeater block
Down-port control block
D1+
D1-
USB Down-port 2
transceiver
D2+
D2-
(3) CPU interface block (CIF)
The CPU interface block performs the following processes.
Control of repeater/down-port states through registers.
Generates interrupt signal
Controls internal bus interface
Fig. 88 HUB function control circuit block diagram
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