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參數(shù)資料
| 型號(hào)： | M38K27M4-XXXHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 80/160頁 |
| 文件大?。?/td> | 2177K |
| 代理商： | M38K27M4-XXXHP |
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25
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38K2 Group
USB FUNCTION
38K2 Group is equipped with a USB function control circuit
(USBFCC) that enables effective interfacing with the host-PC.
This circuit is in compliance with USB2.0's Full-Speed Transfer
Mode (12 Mbps, equivalent to USB1.1). This circuit also supports
all four transfer-types specified in the standard USB specification.
The USBFCC has two USB addresses and 6 endpoints, enabling
separate control of the HUB functions and peripheral functions.
The USB address for HUB functions is equipped with two end-
points. Each endpoint is fixed to a specified transfer type:
Endpoint 0 is fixed to Control Transfer and Endpoint 1 is fixed to
Interrupt Transfer.
The USB address for peripheral functions is equipped with four
endpoints that can select its transfer type. Although Endpoint 0 is
fixed to Control Transfer, the Endpoints 1 to 3 can be set to Inter-
rupt Transfer, Bulk Transfer, or Isochronous Transfer.
A dedicated circuit automatically performs stage management for
Control Transfer and packet management for transactions, which
are necessary for matching of data transmit/receive timing, error
detection, and retry after error. This dedicated control circuit en-
ables the user to develop a program or timing design very easily.
Each endpoint can be programmed for data transfer conditions so
that the endpoints are adaptive for all USB device class transfer
systems.
The data buffer of each endpoint can be assigned to any area in
the multi-channel RAM. This feature offers highly efficient memory
usage by avoiding re-buffering and enabling simple data modifica-
tion.
The transmit/receive data is directly transferred to the data buffer
via the control circuit (direct RAM access type) without disturbing
the CPU operation. This mechanism enables the CPU to transfer
data smoothly with no drop in performance. In addition to this
buffer function, a double-buffer setting will keep a re-buffering stall
at a minimum and increase the overall data throughput (max. 64
bytes X 2 channels).
As other special signals control, the endpoints have detection
functions for the USB bus reset signal, resume signal, suspend
signal, and SOF signal, and also have a remote wake-up signal
transmit function.
When completing data transfer or receiving a special signal, the
endpoint generates the corresponding interrupt to the CPU (3 vec-
tors/24 factors).
With all this essential yet comprehensive built-in hardware, your
system using the 38K2 group will be ready for any USB applica-
tion that comes its way.
USB Data Transfer
The USB specification promises 12 Mbps data transfer in the full-
speed mode, that is equivalent to 1.5 M bytes per second of data
transactions.
However, in USB data transfer, bit-stuffing may be executed de-
pending on the bit patterns of the transfer data, possibly resulting
in 1-byte data (normally 8 bits) handled as up to 10 bits.
Because USB uses asynchronous transfers, the clock cycle of the
USB internal reference clock may change to adjust to the clock
phase. Therefore, the access timing of the USBFCC for the multi-
channel RAM will change owing to the frequency of internal clock
φ:
When the USBFCC is operating at
φ =8 MHZ, access for a normal
transfer is performed every 5 to 6 cycles and access for a bit-stuff-
ing transfer is performed in up to 7 cycles.
If the EXB function is enabled in the above conditions, this func-
tion generates a maximum wait of 1 clock cycle, so that the
access is performed every 4 to 8 cycles.
When operating at
φ = 6MHZ, a normal access is performed every
4 cycles. If the clock-phase correction of the reference clock oc-
curs, access is performed every 3 to 5 cycles.
If bit stuffing occurs at this clock rate, the access cycle will be ex-
tended to up to 6 cycles. When the EXB function that generates a
maximum 1-wait cycle is used in this condition, the access cycle
will be 2 (min.) to 7 (max.) cycles.
Interrupt request
Data transmit/Receive path
[Direct RAM Access Type]
38K2 Group MCU
USB Bus
(USB-Host)
Exter
nal
MCU
CPU
Program ROM
USB
Multi-channel RAM
Built-in Peripheral
Functions
External Bus Interface
(EXB)
Fig. 23 USB function overview
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