參數(shù)資料
型號(hào)： M38K09F8LFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 98/133頁
文件大?。?/td> 1359K
代理商： M38K09F8LFP
38K0 Group
Rev.3.00
Oct 05, 2006
page 67 of 129
REJ03B0192-0300
TC
#0
#1
Mch_req
#0
#1
012
3
(5)
5
req
010016
010116
010216
ack
DMA acknowledge
ExDACK
mWR
detection
mWR
detection
DMA request
ExDREQ
’
’
’
Address ExA0
Chip select ExCS
Terminal count ExTC
Write ExWR
Data DQ0 to DQ7
Internal clock
φ
Operation enabled
Receive buffer RxBuf
TC synchronizing
TC end
Main sequencer
Internal memory access
Memory address
Counter end
Burst end
Memory channel operation
end interrupt
mTC
detection
<Initial setting>
External I/O configuration register
Set as necessary.
Memory channel operation mode register
MC_DIR[1:0] (Memory channel direction control) = 012 (Receive mode)
Burst (burst) = “1” (Burst mode)
Memory address counter
(Example) 010016
End address register
(Example) 010716
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
When a rise of TC is detected, negation of the memory channel request which synchronized with a rise of φ is made.
When the write operation to the end address has been completed, the memory channel operation end interrupt is generated.
Acknowledgment of
internal memory access
Dack =
“0”
A0 = “x”
CS = “1”
Dack =
“0”
A0 = “x”
CS = “1”
(5) Memory Channel Receiving Operation (3)-
Burst Mode (Terminal Count)
Memory channel receiving operation (3) is shown bellow.
Fig. 96 Memory channel receiving operation (3)
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