參數(shù)資料
型號(hào)： M38K07M4L-XXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64
文件頁(yè)數(shù)： 77/90頁(yè)
文件大小： 1410K
代理商： M38K07M4L-XXXFP
Page 79 of 85
Switching Characteristics
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85
°C unless otherwise specified)
Table 5.53
Memory Expansion Mode and Microprocessor Mode (when accessing external
memory space with multiplexed bus)
NOTES:
1. Values, which depend on BCLK frequency, can be obtained from the following equations.
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
3. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
4. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
5. tc [ns] is added when recovery cycle is inserted.
Symbol
Parameter
Measurement
Condition
Standard
Unit
Min.
Max.
td(BCLK-AD)
Address output delay time
18
ns
th(BCLK-AD)
Address output hold time (BCLK standard)
-3
ns
th(RD-AD)
Address output hold time (RD standard)(5)
(note 1)
ns
th(WR-AD)
Address output hold time (WR standard)(5)
(note 1)
ns
td(BCLK-CS)
Chip-select signal output delay time
18
ns
th(BCLK-CS)
Chip-select signal output hold time (BCLK standard)
-3
ns
th(RD-CS)
Chip-select signal output hold time (RD standard)(5)
(note 1)
ns
th(WR-CS)
Chip-select signal output hold time (WR standard)(5)
(note 1)
ns
td(BCLK-RD)
RD signal output delay time
18
ns
th(BCLK-RD)
RD signal output hold time
-5
ns
td(BCLK-WR)
WR signal output delay time
18
ns
th(BCLK-WR)
WR signal output hold time
0
ns
td(DB-WR)
Data output delay time (WR standard)
(note 2)
ns
th(WR-DB)
Data output hold time (WR standard)(5)
(note 1)
ns
td(BCLK-ALE)
ALE signal output delay time (BCLK standard)
18
ns
th(BCLK-ALE)
ALE signal output hold time (BCLK standard)
-2
ns
td(AD-ALE)
ALE signal output delay time (address standard)
(note 3)
ns
th(ALE-AD)
ALE signal output hold time (address standard)
(note 4)
ns
tdz(RD-AD)
Address output float start time
8
ns
109
f(BCLK) × 2
- 10 [ns]
th(RD-AD)
=
109
f(BCLK) × 2
- 15 [ns]
th(WR-AD) =
109
f(BCLK) × 2
- 10 [ns]
th(RD-CS)
=
109
f(BCLK) × 2
- 10 [ns]
th(WR-CS) =
109
f(BCLK) × 2
- 20 [ns]
th(WR-DB) =
109 × m
f(BCLK) × 2
- 25 [ns] (if external bus cycle is a
φ + bφ, m = (b × 2) - 1)
td(DB-WR) =
109 × n
f(BCLK) × 2
- 20 [ns] (if external bus cycle is a
φ + bφ, n = a)
td(AD-ALE) =
109 × n
f(BCLK) × 2
- 20 [ns] (if external bus cycle is a
φ + bφ, n = a)
th(ALE-AD) =
VCC1 = VCC2 = 3.3 V
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PDF描述
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