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參數(shù)資料
| 型號(hào)： | M38D59TFFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 6.25 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 20 X 14 MM. 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁(yè)數(shù)： | 8/13頁(yè) |
| 文件大?。?/td> | 518K |
| 代理商： | M38D59TFFP |
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Rev.1.00
Dec 20, 2006
Page 4 of 37
REJ03B0197-0100
38D5 Group (Flash Memory Version For Development)
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, the
internal system clock control bits, etc.
The CPU mode register is allocated at address 003B16. The flash
memory version do not have the OSCSEL pin. In the single-chip
mode, use this register under low of the CNVss pin.
Only the on-chip oscillator starts oscillation. The XIN-XOUT
oscillation stops oscillating, and XCIN and XCOUT pins function
as I/O ports. The operating mode is the on-chip oscillator mode.
When the low-speed and XIN mode is used, after the XIN-XOUT
oscillation and the XCIN-XCOUT oscillation are enabled, wait in
the on-chip oscillator mode etc. until the oscillation stabilizes,
and then switch the operation mode.
When the XIN mode is not used (XIN-XOUT oscillation and an
external clock input are not used), connect the XIN pin to VCC
through a resistor and leave XOUT open.
CPUM2
The CPU mode register 2 contains the control bits for the on-chip
oscillator.
The CPU mode register 2 is allocated at address 001116.
Fig 3.
Structure of CPU mode register
Fig 4.
Switch procedure of CPU mode register
On-chip oscillator stop bit (Note 1)
0 : Oscillating
1 : Stopped
Not used (returns “0” when read)
(Do not write “1” to this bit)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 :
1 1 :
Stack page selection bit
0 : 0 page
1 : 1 page
Internal system clock selection bit
0 : Main clock selected
(includes OCO, XIN)
1 : XCIN–XCOUT selected
Port Xc switch bit
0 : I/O port function (Oscillation stop)
1 : XCIN–XCOUT oscillating function
XIN–XOUT oscillation stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bit
(Valid only when CM3=0)
(Note 2)
0 0 : f(XIN)/2 (frequency/2 mode)
0 1 : f(XIN)/8 (frequency/8 mode)
1 0 : f(XIN)/4 (frequency/4 mode)
1 1 : On-chip oscillator
b7
b0
CPU mode register 2
CPUM2
(address 001116, OSCSEL=L, initial value: 0016)
(
OSCSEL=H, initial value: 0116)
CM8
b7
b0
CPU mode register
CPUM
(address 003B16, initial value: E016)
CM0
CM1
CM2
CM3
CM4
CM5
CM6
CM7
Not available
Notes 1: When the on-chip oscillator is selected by the watchdog timer count source selection bit 2
(bit 5 of watchdog timer control register (address 002916)), the on-chip oscillator is not
stopped even when the on-chip oscillator stop bit is “1”.
2: 12.5 MHz
< f(XIN)
≤ 16 MHz is not available in the frequency/2 mode.
After releasing reset
N
Y
Low/XIN mode ?
Start the oscillation
(bits 4 and 5 of CPUM)
Oscillator starts oscillation.
Do not change bit 3, bit 6 and bit 7 of CPUM until
oscillation stabilizes.
Select internal system clock
(bit 3 of CPUM or bit 7, 6 = “01”)
Wait by on-chip oscillator operation until
establishment of oscillator clock
Switch the main clock division ratio
selection bit (bit 7, 6 = “00” or “10”)
Start with an on-chip oscillator.
Initial value of CPUM is E016.
Initial value of CPUM2 is 0016.
As for the details of condition for
transition among each mode,
refer to the state transition of system clock.
System can operate in on-chip oscillator mode until
oscillation stabilize.
Select internal system clock.
Do not change bit 3, bit 6 and bit 7 of CPUM at the
same time.
Select main clock division ratio.
Switch to frequency/2 or 4 mode here, if necessary.
Main routine
Reset
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