參數(shù)資料
型號: M38D24G4HP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 6.25 MHz, MICROCONTROLLER, PQFP64
封裝: 10X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù): 24/136頁
文件大?。?/td> 2856K
代理商: M38D24G4HP
Rev.3.02
Apr 10, 2008
Page 12 of 131
REJ03B0177-0302
38D2 Group
Fig. 6 Register push and pop at interrupt generation and subroutine call
Interrupt request
On-going Routine
M(S) (PCH)
(S) (S)
1
M(S) (PCL)
(S) (S)
1
....
.
Execute RTS
Subroutine
(S) (S) + 1
(PCL) M(S)
(S) (S) + 1
(PCH) M(S)
M(S) (PCH)
(S) (S)
1
M(S) (PCL)
(S) (S)
1
M(S) (PS)
(S) (S)
1
Interrupt Service
Routine
(S) (S)
+ 1
(PS) M(S)
(S) (S)
+ 1
(PCL) M(S)
(S) (S)
+ 1
(PCH) M(S)
Execute JSR
Execute RTI
(1)
Push return address
on stack
Push contents of processor
status register on stack
I Flag is set from “0” to “1”
Fetch the jump vector
POP contents of
processor status
register from stack
POP return
address
from stack
POP return address
from stack
Push return address
on stack
Note1: Condition for acceptance of an interrupt request here
→ Interrupt disable flag is “0” and
Interrupt enable bit corresponding to each interrupt source is “1”
--
-
Table 6
Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PLA
Processor status register
PHP
PLP
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