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參數(shù)資料
| 型號(hào)： | M38C37ECMFS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, UVPROM, 4 MHz, MICROCONTROLLER, CQCC80 |
| 封裝： | 0.80 MM PITCH, CERAMIC, LCC-80 |
| 文件頁(yè)數(shù)： | 63/221頁(yè) |
| 文件大?。?/td> | 1919K |
| 代理商： | M38C37ECMFS |
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Interrupt Controller Operation
Interrupt Controller
9-5
NOTE:
The MC68VZ328 supports the reset instruction. However, it only resets the
CPU, and the RESET pin will not go low when this instruction is issued
because it is an input-only signal.
The MC68VZ328’s RESET signal should be held low for at least 1.2 s after VDD is applied. See
Section 4.3.2.1, “PLLCLK Initial Power-up Sequence,” on page 4-5 for detailed information about
selecting the optimum RESET delay. After reset, all peripheral function signals and parallel I/O signals
appear as inputs with pull-up resistors turned on, unless otherwise specified. The multiplexed, parallel I/O
D[7:0]/PA[7:0] function is controlled by the WDTH8 bit in the system control register. If the value of
WDTH8 is 0, it is D[7:0]. If WIDTH8 is 1, it is PA[7:0].
9.3.1 Operation Mode Selection During Reset
The MC68VZ328 supports three modes of operation: normal mode, emulation mode, and bootstrap mode.
The selection of the modes is controlled by the EMUIRQ, EMUBRK, and HIZ signals during system reset,
so special attention should be paid when using these signals. Refer to Chapter 2, “Signal Descriptions,” for
more information.
9.3.2 Data Bus Width for Boot Device Operation
The word size of the boot device (ROM/EPROM/FLASH) is determined by the BUSW signal. If it is high
during the rising edge of the RESET signal, the 16-bit boot device will be configured. Otherwise, it will be
configured as an 8-bit boot device.
9.4 Interrupt Controller Operation
When interrupts are received by the controller, they are prioritized, and the highest enabled, pending
interrupt is posted to the CPU. Before the CPU responds to this interrupt, the status register is copied
internally, and then the supervisor bit of the CPU status register is set, placing the processor into supervisor
mode. The CPU then responds with an interrupt acknowledge cycle in which the lower 3 bits of the address
bus reflect the priority level of the current interrupt. The interrupt controller generates a vector number
during the interrupt acknowledge cycle, and the CPU uses this vector number to generate a vector address.
Except for the reset exception, the CPU saves the current processor status, including the program counter
value (which points to the next instruction to be executed after the interrupt) and the saved copy of the
interrupt status register. The new program counter is updated to the content of the interrupt vector, which
points to the interrupt service routine. The CPU then resumes instruction execution to execute the interrupt
service routine.
9.4.1 Interrupt Priority Processing
Interrupt priority is based on the priority level of the interrupt. If the CPU is currently processing an
interrupt service routine and a higher priority interrupt is posted, the process described in Section 9.4,
“Interrupt Controller Operation,” repeats, and the higher priority interrupt is serviced. If the priority of the
newer interrupt is lower than or equal to the priority of the current interrupt, execution of the current
interrupt handler continues. The newer interrupt is postponed until its priority becomes the highest.
Interrupts within the same level should be prioritized in software by the interrupt handler. The interrupt
service routine should end with the rte instruction, which restores the processing state prior to the interrupt.
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