8
38C3 Group User’s Manual
List of figures
Fig. 3.5.16 Structure of Timer 34 mode register ..................................................................... 3-47
Fig. 3.5.17 Structure of Timer 56 mode register ..................................................................... 3-47
Fig. 3.5.18 Structure of
φ output control register .................................................................... 3-48
Fig. 3.5.19 Structure of Timer A register (low-order, high-order) ......................................... 3-48
Fig. 3.5.20 Structure of Compare register (low-order, high-order) ........................................ 3-49
Fig. 3.5.21 Structure of Timer A mode register ...................................................................... 3-49
Fig. 3.5.22 Structure of Timer A control register .................................................................... 3-50
Fig. 3.5.23 Structure of A-D control register ............................................................................ 3-50
Fig. 3.5.24 Structure of A-D conversion register (low-order) ................................................. 3-51
Fig. 3.5.25 Structure of A-D conversion register (high-order) ............................................... 3-51
Fig. 3.5.26 Structure of Segment output enable register ....................................................... 3-52
Fig. 3.5.27 Structure of LCD mode register ............................................................................. 3-52
Fig. 3.5.28 Structure of Interrupt edge selection register ...................................................... 3-53
Fig. 3.5.29 Structure of CPU mode register ............................................................................ 3-53
Fig. 3.5.30 Structure of Interrupt reqeust register 1 ............................................................... 3-54
Fig. 3.5.31 Structure of Interrupt request register 2 ............................................................... 3-55
Fig. 3.5.32 Structure of Interrupt control register 1 ................................................................ 3-56
Fig. 3.5.33 Structure of Interrupt control register 2 ................................................................ 3-56
Fig. 3.5.34 Structure of ROM correct enable register 1 ......................................................... 3-57