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參數(shù)資料
| 型號： | M38C35E7MXXXFS |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 16/62頁 |
| 文件大?。?/td> | 881K |
| 代理商： | M38C35E7MXXXFS |
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16
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C3 Group
Interrupt Source
Reset
(Note 2)
INT
0
INT
1
INT
2
Serial I/O
Timer A
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
CNTR
0
CNTR
1
Key input (Key-
on wake-up)
A-D conversion
BRK instruction
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Vector Addresses
(Note 1)
High
FFFD
16
FFFB
16
FFF9
16
FFF7
16
FFF5
16
FFF3
16
FFF1
16
FFEF
16
FFED
16
FFEB
16
FFE9
16
FFE7
16
FFE5
16
FFE3
16
FFE1
16
FFDF
16
FFDD
16
Interrupt Request
Generating Conditions
At reset
At detection of either rising or falling edge of
INT
0
intput
At detection of either rising or falling edge of
INT
1
input
At detection of either rising or falling edge of
INT
2
input
At completion of serial I/O data transmit/re-
ceive
At timer A underflow
At timer 1 underflow
At timer 2 underflow
At timer 3 underflow
At timer 4 underflow
At timer 5 underflow
At timer 6 underflow
At detection of either rising or falling edge of
CNTR
0
input
At detection of either rising or falling edge of
CNTR
1
input
At falling of port P8 (at input) input logical level
AND
At completion of A-D conversion
At BRK instruction execution
Remarks
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O is selected
STP release timer underflow
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(falling valid)
Valid when A-D conversion interrupt
is selected
Non-maskable software interrupt
Low
FFFC
16
FFFA
16
FFF8
16
FFF6
16
FFF4
16
FFF2
16
FFF0
16
FFEE
16
FFEC
16
FFEA
16
FFE8
16
FFE6
16
FFE4
16
FFE2
16
FFE0
16
FFDE
16
FFDC
16
Notes 1:
Vector addresses contain interrupt jump destination addresses.
2:
Reset function in the same way as an interrupt with the highest priority.
Table 6 Interrupt vector addresses and priority
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