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參數(shù)資料
| 型號： | M38C29FFFP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 30/63頁 |
| 文件大?。?/td> | 1000K |
| 代理商： | M38C29FFFP |
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30
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
SERIAL I/O
The 38C2 group has built-in two 8-bit serial I/O.
Serial I/O can be used as either clock synchronous or asynchronous
(UART) serial I/O. A dedicated timer is also provided for baud rate
generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
serial I/O mode selection bit of the serial I/O control register to
“
1
”
.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Fig. 25 Block diagram of clock synchronous serial I/O
Fig. 26 Operation of clock synchronous serial I/O function
1/4
1/4
F/F
P5
6
/S
CLK1
[P3
1
/S
CLK2
]
Serial I/O status register
Serial I/O control register
P5
7
/S
RDY1
[P3
0
/S
RDY2
]
P5
4
/R
X
D
1
[P3
3
/R
X
D
2
]
P5
5
/T
X
D
1
[P3
2
/T
X
D
2
]
f(X
IN
)
(f(X
CIN
) in low-speed mode)
Receive buffer register
Address 001C
16
[Address 001E
16
]
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Clock control circuit
Shift clock
Serial I/O synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
Address 0FE2
16
[Address 0FE5
16
]
BRG count source selection bit
Clock control circuit
Falling-edge detector
Transmit buffer register
Data bus
Address 001C
16
[Address 001E
16
]
Shift clock
Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Address 001D
16
[Address 001F
16
]
Transmit interrupt request (TI)
Transmit interrupt source selection bit
Data bus
16
Address 0FE0
16
]
Transmit shift register
[ ] : For Serial I/O2
D
7
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
0
D
1
D
2
D
3
D
4
D
5
D
6
RBF = 1
TSC = 1
Overrun error (OE)
detection
TBE = 0
TBE = 1
TSC = 0
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
Serial input RxD
Write pulse to receive/transmit
buffer register
Notes 1:
As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O
control register.
2:
If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the TxD pin.
3:
The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes
“
1
”
.
Receive enable signal
S
RDY
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