參數(shù)資料
型號(hào)： M38C24M6-XXXHP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP64
封裝： 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁(yè)數(shù)： 31/91頁(yè)
文件大?。?/td> 1867K
代理商： M38C24M6-XXXHP
36
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
LCD DRIVE CONTROL CIRCUIT
The 38C2 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
LCD display RAM
Segment output disable register
LCD mode register
Selector
Timing controller
Common driver
Segment driver
Bias control circuit
A maximum of 24 segment output pins and 4 common output pins
can be used.
Up to 96 pixels can be controlled for an LCD display. When the LCD
enable bit is set to “1” after data is set in the LCD mode register, the
Fig. 32 Structure of LCD related registers
segment output disable register, and the LCD display RAM, the LCD
drive control circuit starts reading the display data automatically, per-
forms the bias control and the duty ratio control, and displays the
data on the LCD panel.
Table 8 Maximum number of display pixels at each duty ratio
Duty ratio
2
3
4
Maximum number of display pixels
48 dots
or 8 segment LCD 6 digits
72 dots
or 8 segment LCD 9 digits
96 dots
or 8 segment LCD 12 digits
Segment output disable bit 0
0 : Segment output SEG0
1 : Output port P00
Segment output disable bit 1
0 : Segment output SEG1
1 : Output port P01
Segment output disable bit 2
0 : Segment output SEG2
1 : Output port P02
Segment output disable bit 3
0 : Segment output SEG3
1 : Output port P03
Segment output disable bit 4
0 : Segment output SEG4
1 : Output port P04
Segment output disable bit 5
0 : Segment output SEG5
1 : Output port P05
Segment output disable bit 6
0 : Segment output SEG6
1 : Output port P06
Segment output disable bit 7
0 : Segment output SEG7
1 : Output port P07
Segment output disable register 0
(SEG0 : address 0FF816)
b7
b0
LCD mode register
(LM : address 003916)
Duty ratio selection bits
b1 b0
0 0 : Not used
0 1 : 2 (use COM0,COM1)
1 0 : 3 (use COM0–COM2)
1 1 : 4 (use COM0–COM3)
Bias control bit
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
LCD drive timing selection bit
0 : Type A
1 : Type B
LCD circuit divider division ratio selection bits
b6 b5
0 0 : Clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit (Note)
0 : f(XCIN)/32
1 : f(XIN)/8192 (f(XCIN)/8192 in low-speed mode)
Note : LCDCK is a clock for an LCD timing controller.
b7
b0
Segment output disable bit 8
0 : Segment output SEG8
1 : Output port P10
Segment output disable bit 9
0 : Segment output SEG9
1 : Output port P11
Segment output disable bit 10
0 : Segment output SEG10
1 : Output port P12
Segment output disable bit 11
0 : Segment output SEG11
1 : Output port P13
Segment output disable bit 12
0 : Segment output SEG12
1 : Output port P14
Segment output disable bit 13
0 : Segment output SEG13
1 : Output port P15
Segment output disable bit 14
0 : Segment output SEG14
1 : Output port P16
Segment output disable bit 15
0 : Segment output SEG15
1 : Output port P17
Segment output disable register 1
(SEG1 : address 0FF916)
b7
b0
Segment output disable bit 16
0 : Output port P20
1 : Segment output SEG16
Segment output disable bit 17
0 : Output port P21
1 : Segment output SEG17
Segment output disable bit 18
0 : Output port P22
1 : Segment output SEG18
Segment output disable bit 19
0 : Output port P23
1 : Segment output SEG19
Segment output disable bit 20
0 : Output port P24
1 : Segment output SEG20
Segment output disable bit 21
0 : Output port P25
1 : Segment output SEG21
Segment output disable bit 22
0 : Output port P26
1 : Segment output SEG22
Segment output disable bit 23
0 : Output port P27
1 : Segment output SEG23
Segment output disable register 2
(SEG2 : address 0FFA16)
b7
b0
Notes 1: Only pins set to output ports by the direction register can be controlled to switch
to output ports or segment outputs by the segment output disable register.
2: When the VL pin input selection bit (VLSEL) of the LCD power control register
(address 003816) is “1”, settings of the segment output disable bit 22 and segment
output disable bit 23 are invalid.
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