參數(shù)資料
型號: M38C13E6HP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PQFP64
封裝: 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù): 30/59頁
文件大?。?/td> 704K
代理商: M38C13E6HP
Rev.2.40
Jun 14, 2004
page 36 of 56
38C1 Group
Fig. 35 Structure of clock output control register
OTHER FUNCTION REGISTERS
q
φ clock output function
The internal clock
φ can be output from port P63 by setting the φ
output control register.
At
φ clock output, set “1” to the bit 3 of the port P6 direction regis-
ter.
b7b0
φ output control register
(CKOUT: address 002A16, initial value: 0016)
φ output control bit
00 :
01 :
10 :
11 :
Port function
φ frequency signal output
XCIN frequency signal output
Not available
Not used (returns “0” when read)
(Do not write “1” to this bit)
b7
b0
DB0 data stored
DB1 data stored
DB2 data stored
DB3 data stored
DB4 data stored
DB5 data stored
DB6 data stored
DB7 data stored
b7b0
RRF register
(RRFR: address 002F16, initial value: 0016)
DB4 data stored
DB5 data stored
DB6 data stored
DB7 data stored
DB0 data stored
DB1 data stored
DB2 data stored
DB3 data stored
Temporary data registers 0, 1, 2
(TD0, TD1, TD2: address 002C16, 002D16, 002E16,
initial value: 0016)
q Temporary data register
The temporary data register (addresses 002C16 to 002E16) is the
8-bit register and does not have the control function. It can be
used to store data temporarily. It is initialized after reset.
q RRF register
The RRF register (address 002F16) is the 8-bit register and does
not have the control function.
As for the value written in this register, high-order 4 bits and low-
order 4 bits interchange.
It is initialized after reset.
Fig. 36 Structure of temporary data register, RRF register
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