參數(shù)資料
型號： M38C13E6FP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, PLASTIC, LQFP-64
文件頁數(shù)： 16/59頁
文件大小： 955K
代理商： M38C13E6FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C1 Group
23
Timer Y
Timer Y is a 16-bit timer that can be selected in one of four modes.
(1) Timer mode
The timer counts the followings;
f(XIN)/16 in middle-, or high-speed mode
f(XCIN)/16 in low-speed mode
f(XROSC) divided by 16 in ring oscillator mode
(2) Period measurement mode
CNTR1 interrupt request is generated at rising/falling edge of
CNTR1 pin input signal. Simultaneously, the value in timer Y latch
is reloaded in timer Y and timer Y continues counting down. Ex-
cept for the above-mentioned, the operation in period measure-
ment mode is the same as in timer mode.
The timer value just before the reloading at rising/falling of CNTR1
pin input signal is retained until the timer Y is read once after the
reload.
The rising/falling timing of CNTR1 pin input signal is found by
CNTR1 interrupt. When using a timer in this mode, set the corre-
sponding port P53 direction register to input mode.
(3) Event counter mode
The timer counts signals input through the CNTR1 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corre-
sponding port P53 direction register to input mode.
(4) Pulse width HL continuously measure-
ment mode
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode. When using a timer in this mode, set
the corresponding port P53 direction register to input mode.
sNote on CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit. However, in pulse width HL continuously measurement
mode, CNTR1 interrupt request is generated at both rising and
falling edges of CNTR1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
Fig. 20 Structure of timer Y mode register
Timer Y mode register
(TYM : address 002816, initial value: 0016)
b7
b0
Not used (returns “0” when read)
(Do not write “1” to these bits.)
Timer Y operating mode bits
b5 b4
0
0 : Timer mode
0
1 : Period measurement mode
1
0 : Event counter mode
1
1 : Pulse width HL continuously
measurement mode
CNTR1 active edge switch bit
0 : Count at rising edge in event counter mode
Measure the falling edge to falling edge
period in period measurement mode
Falling edge active for CNTR1 interrupt
1 : Count at falling edge in event counter mode
Measure the rising edge period in period
measurement mode
Rising edge active for CNTR1 interrupt
Timer Y stop control bit
0 : Count start
1 : Count stop
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