參數(shù)資料
型號(hào): M38C12M4-XXXHP
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP64
封裝: 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁(yè)數(shù): 10/59頁(yè)
文件大?。?/td> 704K
代理商: M38C12M4-XXXHP
Rev.2.40
Jun 14, 2004
page 18 of 56
38C1 Group
INTERRUPTS
Interrupts occur by thirteen sources: five external, seven internal,
and one software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the corre-
sponding interrupt request and enable bits are “1” and the inter-
rupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
s Notes on Interrupts
When the active edge of an external interrupt (INT0 , INT1, CNTR0
or CNTR1) is set or an interrupt source where several interrupt
source is assigned to the same vector address is switched, the
corresponding interrupt request bit may also be set. Therefore,
take following sequence:
(1) Disable the interrupt.
(2) Set the interrupt edge selection register (Timer X control regis-
ter for CNTR0, Timer Y mode register for CNTR1).
(3) Clear the set interrupt request bit to “0.”
(4) Enable the interrupt.
Notes1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Table 6 Interrupt vector addresses and priority
Remarks
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of INT1 input
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 3 underflow
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At timer 2 underflow
At completion of serial I/O data
transmission or reception
At falling of conjunction of input
level for port P3 (at input mode)
At completion of A/D conversion
At BRK instruction execution
Interrupt Source
Low
High
Priority
Vector Addresses (Note 1)
Reset (Note 2)
INT0
INT1
Timer X
Timer Y
Timer 1
Timer 3
CNTR0
CNTR1
Timer 2
Serial I/O
Key input
(Key-on wake-up)
A/D conversion
BRK instruction
1
2
3
4
5
6
7
8
9
10
11
12
13
14
FFFD16
FFFB16
FFF916
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE316
FFE116
FFDF16
FFDD16
FFFC16
FFFA16
FFF816
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE216
FFE016
FFDE16
FFDC16
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(valid at falling)
Valid when A/D interrupt is selected
Non-maskable software interrupt
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