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參數(shù)資料
| 型號(hào)： | M38B5 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Chip 8 Bits Microcomputer(8位單片機(jī)) |
| 中文描述： | 單芯片8位單片機(jī)（8位單片機(jī)） |
| 文件頁數(shù)： | 40/69頁 |
| 文件大?。?/td> | 1011K |
| 代理商： | M38B5 |
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MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
40
PRELIMINARY
Notice: This s not a final specification.
Some parametric imits are subject to change.
Data setup
(1) 16-timingOrdinary Mode
The area of addresses 0FB0
16
to 0FFF
16
are used as a
FLD automatic display RAM.
When data is stored in the FLD automatic display RAM,
the last data of FLD port P2 is stored at address 0FB0
16
,
the last data of FLD port P0 is stored at address 0FC0
16
,
the last data of FLD port P1 is stored at address 0FD0
16
,
the last data of FLD port P3 is stored at address 0FE0
16
,
and the last data of FLD port P8 is stored at address 0FF0
16
,
to assign in sequence from the last data respectively.
The first data of the FLD port P2, P0, P1, P3, and P8 is stored at
an address which adds the value of (the timing number – 1) to the
corresponding address 0FB0
16
, 0FC0
16
, 0FD0
16
, 0FE0
16
, and
0FF0
16
.
Set the FLD data pointer reload register to the value given by the
number of digits – 1. “1” is always written to bit 6, and “0” is
always written to bit 5. Note that “0” is always read from bits 6
and 5 when reading.
(2) 16-timingGradation Display Mode
Display data setting is performed in the same way as that of the
16-timingordinary mode. Gradation display control data is
arranged at an address resulting from subtracting 0050
16
from
the display data store address of each timing and pin. Bright dis-
play is performed by setting “0,” and dark display is performed by
setting “1.”
(3) 32-timing Mode
The area of addresses 0F60
16
to 0FFF
16
are used as a
FLD automatic display RAM.
When data is stored in the FLD automatic display RAM,
the last data of FLD port P2 is stored at address 0F60
16
,
the last data of FLD port P0 is stored at address 0F80
16
,
the last data of FLD port P1 is stored at address 0FA0
16
,
the last data of FLD port P3 is stored at address 0FC0
16
,
and the last data of FLD port P8 is stored at address 0FE0
16
,
to assign in sequence from the last data respectively.
The first data of the FLD port P2, P0, P1, P3, and P8 is stored at
an address which adds the value of (the timing number – 1) to the
corresponding address 0F60
16
, 0F80
16
, 0FA0
16
, 0FC0
16
, and
0FE0
16
.
Set the FLD data pointer reload register to the value given by the
number of digits–1. “1” is always written to bit 6, and “0” is always
written to bit 5. Note that “0” is always read from bits 6 and 5
when reading.
Fig. 43 Example of Using the FLD Automatic Display RAM in
16-timingOrdinary Mode
Number of FLD segments: 15
Address
0FB0
16
0FCF
16
0FD0
16
0FD1
16
0FD2
16
0FD3
16
0FD4
16
0FD5
16
0FD6
16
0FD7
16
0FD8
16
0FD9
16
0FDA
16
0FDB
16
0FDC
16
0FDD
16
0FDE
16
0FDF
16
0FE0
16
0FB1
16
0FB2
16
0FB3
16
0FB4
16
0FB5
16
0FB6
16
0FB7
16
0FB8
16
0FB9
16
0FBA
16
0FBB
16
0FBC
16
0FBD
16
0FBE
16
0FBF
16
0FC0
16
0FC1
16
0FC2
16
0FC3
16
0FC4
16
0FC5
16
0FC6
16
0FC7
16
0FC8
16
0FC9
16
0FCA
16
0FCB
16
0FCC
16
0FCD
16
0FCE
16
0FE1
16
0FE2
16
0FE3
16
0FE4
16
0FE5
16
0FE6
16
0FE7
16
0FE8
16
0FE9
16
0FEA
16
0FEB
16
0FEC
16
0FED
16
0FEE
16
0FEF
16
0FF0
16
0FF1
16
0FF2
16
0FF3
16
0FF4
16
0FF5
16
0FF6
16
0FF7
16
0FF8
16
0FF9
16
0FFA
16
0FFB
16
0FFC
16
0FFD
16
0FFE
16
0FFF
16
shaded area is used for segment.
Note:
(TheThe last timing
7
6
5
4
3
2
1
0
Bit
(TheThe last timing
(TheThe last timing
(TheThe last timing
The last timing
(The last data of FLDP8)
(TheTiming for start
FLDP2 data area
(TheTiming for start
FLDP0 data area
(TheTiming for start
FLDP1 data area
(TheTiming for start
FLDP3 data area
(TheTiming for start
FLDP8 data area
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