參數(shù)資料
型號(hào)： M38B57MC-XXXFP
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4.19 MHz, MICROCONTROLLER, PQFP80
封裝： 0.80 MM PITCH, PLASTIC, QFP-80
文件頁(yè)數(shù)： 39/70頁(yè)
文件大?。?/td> 1041K
代理商： M38B57MC-XXXFP
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
43
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
Digit data protect function
The FLD automatic display RAM is provided with a data protect
function that disables the RAM area data to be rewritten as digit
data.
This function can disable data from being written in optional bits in
the RAM area corresponding to P1 to P3. A programming load can
be reduced by protecting an area that requires no change after
data such as digit data is written.
Write digit data beforehand; then set “1” in the corresponding bits.
With this, the setting is completed.
The data protect area becomes the maximum RAM area of P1 and
P3. For example, when bit 0 of P1 is protected in the 16-
timingordinary mode, bits 0 of RAM addresses 0FD016 to 0FDF16
can be protected. Likewise, in the 16-timinggradation display mode,
bits 0 of addresses 0FD016 to 0FDF16 and 0F8016 to 0F8F16 can be
protected. In the 32-timing mode, bits 0 of addresses 0FA016 to
0FBF16 can be protected.
Fig. 46 Structure of FLDRAM Write Disable Register
b7
b0
P1FLDRAM write disable register
(P1FLDRAM : address 0EF216)
FLDRAM corresponding to P10
FLDRAM corresponding to P11
FLDRAM corresponding to P12
FLDRAM corresponding to P13
FLDRAM corresponding to P14
FLDRAM corresponding to P15
FLDRAM corresponding to P16
FLDRAM corresponding to P17
b7
b0
0: Operating normally
1: Write disabled
P3FLDRAM write disable register
(P3FLDRAM : address 0EF316)
FLDRAM corresponding to P30
FLDRAM corresponding to P31
FLDRAM corresponding to P32
FLDRAM corresponding to P33
FLDRAM corresponding to P34
FLDRAM corresponding to P35
FLDRAM corresponding to P36
FLDRAM corresponding to P37
0: Operating normally
1: Write disabled
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