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| 型號： | M38B57M6-147FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SENSOR SST 5/8 HALL EFFECT |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 29/69頁 |
| 文件大?。?/td> | 1011K |
| 代理商： | M38B57M6-147FP |
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MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
29
PRELIMINARY
Notice: This s not a final specification.
Some parametric imits are subject to change.
When the external synchronous clock is selected, input an “H” level
signal into the S
BUSY1
input and an “L” level signal into the S
BUSY1
input in the initial status in which transfer is stopped. At this time,
the transfer clocks to be input in S
CLK1
become invalid.
During serial transfer, the transfer clocks to be input in S
CLK1
be-
come valid, enabling a transmit/receive operation, while an “L” level
signal is input into the S
BUSY1
input and an “H” level signal is input
into the S
BUSY1
input.
When changing the input values in the S
BUSY1
input and the S
BUSY1
input at these operations, change them when the S
CLK1
input is in a
high state.
When the high impedance of the S
OUT1
output is selected by the
S
OUT1
pin control bit (b6), the S
OUT1
output becomes active, en-
abling serial transfer by inputting a transfer clock to S
CLK1
, while an
“L” level signal is input into the S
BUSY1
input and an “H” level signal
is input into the S
BUSY1
input.
__________
3. S
BUSY1
output signal
The S
BUSY1
output is a signal which requests a stop of transmis-
sion/reception to the serial transfer destination. In the automatic
transfer serial I/O mode, regardless of the internal or external syn-
chronous clock, whether the S
BUSY1
output is to be active at trans-
fer of each 1-byte data or during transfer of all data can be selected
by the S
BUSY1
output S
STB1
output function selection bit (b4).
In the initial status, the status in which the serial I/O initialization bit
(b4) is reset to “0,” the S
BUSY1
output goes to “H” and the S
BUSY1
output goes to “L.”
Fig. 25 S
BUSY1
Input Operation (internal synchronous clock)
Fig. 26 S
BUSY1
Input Operation (external synchronous clock)
(4) Handshake Signal
1. S
STB1
output signal
The S
STB1
output is a signal to inform an end of transmission/re-
ception to the serial transfer destination . The S
STB1
output signal
can be used only when the internal synchronous clock is selected.
In the initial status, namely, in the status in which the serial I/O
initialization bit (b4) is reset to “0,” the S
STB1
output goes to “L,” or
the S
STB1
output goes to “H.”
At the end of transmit/receive operation, when the data of the serial
I/O1 register is all output from S
OUT1
, pulses are output in the pe-
riod of 1 cycle of the transfer clock so as to cause the S
STB1
output
to go “H” or the S
STB1
output to go “L.” After that, each pulse is
STB1
output goes to “L” or the
________
STB1
output goes to “H.”
Furthermore, after 1 cycle, the serial transfer status flag (b5) is re-
set to “0.”
In the automatic transfer serial I/O mode, whether the S
STB1
output
is to be active at an end of each 1-byte data or after completion of
transfer of all data can be selected by the S
BUSY1
output S
STB1
output function selection bit (b4 of address 001A
16
) of serial I/O1
control register 2.
2. S
BUSY1
input signal
The S
BUSY1
input is a signal which receives a request for a stop of
transmission/reception from the serial transfer destination.
When the internal synchronous clock is selected, input an “H” level
signal into the S
BUSY1
input and an “L” level signal into the S
BUSY1
input in the initial status in which transfer is stopped.
When starting a transmit/receive operation, input an “L” level signal
into the S
BUSY1
input and an “H” level signal into the S
BUSY1
input in
the period of 1.5 cycles or more of the transfer clock. Then, transfer
clocks are output from the S
CLK1
output.
When an “H” level signal is input into the S
BUSY1
input and an “L”
level signal into the S
BUSY1
input after a transmit/receive operation
is started, this transmit/receive operation are not stopped immedi-
ately and the transfer clocks from the S
CLK1
output is not stopped
until the specified number of bits are transmitted and received.
The handshake unit of the 8-bit serial I/O is 8 bits and that of the
automatic transfer serial I/O is 8 bits.
Fig. 24 S
STB1
Output Operation
S
STB1
S
CLK1
S
OUT1
Serial transfer
status flag
S
BUSY1
S
CLK1
S
OUT1
S
BUSY1
S
CLK1
S
OUT1
Invalid
(Output high-impedance)
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