參數(shù)資料
型號： M38B57M6-123FP
廠商： Mitsubishi Electric Corporation
英文描述： TACHOMETER ONE CHANNEL
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 57/69頁
文件大?。?/td> 1011K
代理商： M38B57M6-123FP
MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
57
PRELIMINARY
Notice: This s not a final specification.
Some parametric imits are subject to change.
Clock Generating Circuit
The 38B5 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between X
IN
and
X
OUT
(X
CIN
and X
COUT
). Use the circuit constants in accordance with
the resonator manufacturer's recommended values. No
external resistor is needed between X
IN
and X
OUT
since a feedback
resistor exists on-chip. However, an external feedback resistor is
needed between X
CIN
and X
COUT
.
Immediately after power on, only the X
IN
oscillation circuit starts
oscillating, and X
CIN
and X
COUT
pins function as I/O ports.
G
Frequency control
(1) Middle-speed mode
The internal system clock is the frequency of X
IN
divided by 4. After
reset, this mode is selected.
(2) High-speed mode
The internal system clock is the frequency of X
IN
.
(3) Low-speed mode
The internal system clock is the frequency of X
CIN
divided by 2.
I
Note
If you switch the mode between middle/high-speed and low-speed,
stabilize both X
IN
and X
CIN
oscillations. The sufficient time is required
for the sub clock to stabilize, especially immediately after power on
and at returning from stop mode. When switching the mode between
middle/high-speed and low-speed, set the frequency on condition
that f(X
IN
) > 3f(X
CIN
).
(4) Low power consumption mode
The low power consumption operation can be realized by stopping
the main clock X
IN
in low-speed mode. To stop the main clock, set bit
5 of the CPU mode register to “1.” When the main clock X
IN
is re-
started (by setting the main clock stop bit to “0”), set enough time for
oscillation to stabilize.
By clearing furthermore the X
COUT
drivability selection bit (b3) of CPU
mode register to “0,” low power consumption operation of less than
200 μA (f(X
CIN
) = 32 kHz) can be realized by reducing the drivability
between X
CIN
and X
COUT
. At reset or during STP instruction execu-
tion this bit is set to “1” and a strong drivability that has an easy
oscillation start is set.
G
Oscillation control
(1) Stop mode
If the STP instruction is executed, the internal system clock stops at
an “H” level, and X
IN
and X
CIN
oscillators stop. Timer 1 is set to “FF
16
”
and timer 2 is set to “01
16
.”
Either X
IN
divided by 8 or X
CIN
divided by 16 is input to timer 1 as
count source, and the output of timer 1 is connected to timer 2. The
bits of the timer 12 mode register are cleared to “0.” Set the interrupt
enable bits of the timer 1 and timer 2 to disabled (“0”) before execut-
ing the STP instruction. Oscillator restarts when an external interrupt
is received, but the internal system clock is not supplied to the CPU
until timer 1 underflows. This allows time for the clock circuit oscilla-
tion to stabilize.
(2) Wait mode
If the WIT instruction is executed, the internal system clock stops at
an “H” level. The states of X
IN
and X
CIN
are the same as the state
before executing the WIT instruction. The internal system clock re-
starts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after the
clock is restarted.
Fig. 68 Ceramic Resonator Circuit
Fig. 69 External Clock Input Circuit
X
IN
X
OUT
External oscillation circuit
V
CC
V
SS
open
X
CIN
X
COUT
External oscillation circuit
or external pulse
V
CC
open
V
SS
X
CIN
X
COUT
X
IN
X
OUT
C
IN
C
OUT
C
CIN
C
COUT
Rf
Rd
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