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    參數(shù)資料
    型號: M38B50M2XXXFP
    廠商: Renesas Technology Corp.
    英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
    中文描述: 單芯片8位CMOS微機
    文件頁數(shù): 32/70頁
    文件大?。?/td> 864K
    代理商: M38B50M2XXXFP
    MITSUBISHI MICROCOMPUTERS
    38B5 Group
    SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
    31
    PRELIMINARY
    Notice: This s not a final specification.
    Some parametric imits are subject to change.
    4. S
    RDY1
    output signal
    The S
    RDY1
    output is a transmit/receive enable signal which informs
    the serial transfer destination that transmit/receive is ready. In the
    initial status, when the serial I/O initialization bit (b4) is reset to “0,”
    the S
    RDY1
    output goes to “L” and the S
    RDY1
    output goes to “H”. After
    transmitted data is stored in the serial I/O1 register (address 001B
    16
    )
    and a transmit/receive operation becomes ready, the S
    RDY1
    output
    goes to “H” and the S
    RDY1
    output goes to “L”. When a transmit/
    receive operation is started and the transfer clock goes to “L”, the
    S
    RDY1
    output goes to “L” and the S
    RDY1
    output goes to “H”.
    5. S
    RDY1
    input signal
    The S
    RDY1
    input signal becomes valid only when the S
    RDY1
    input
    and the S
    BUSY1
    output are used. The S
    RDY1
    input is a signal for
    receiving a transmit/receive ready completion signal from the serial
    transfer destination.
    When the internal synchronous clock is selected, input a low level
    signal into the S
    RDY1
    input and a high level signal into the S
    RDY1
    input in the initial status in which the transfer is stopped.
    When an “H” level signal is input into the S
    RDY1
    input and an “L”
    level signal is input into the S
    RDY1
    input for a period of 1.5 cycles or
    more of transfer clock, transfer clocks are output from the S
    CLK1
    output and a transmit/receive operation is started.
    After the transmit/receive operation is started and an “L” level sig-
    RDY1
    input and an “H” level signal into the
    _________
    RDY1
    input, this operation cannot be immediately stopped.
    After the specified number of bits are transmitted and received, the
    transfer clocks from the S
    CLK1
    output is stopped. The handshake
    unit of the 8-bit serial I/O and that of the automatic transfer serial
    I/O are of 8 bits.
    When the external synchronous clock is selected, the S
    RDY1
    input
    becomes one of the triggers to output the S
    BUSY1
    signal.
    To start a transmit/receive operation (S
    BUSY1
    output: “L,” S
    BUSY1
    output: “H”), input an “H” level signal into the S
    RDY1
    input and an “L”
    level signal into the S
    RDY1
    input, and also write transmit data into
    the serial I/O1 register.
    _________
    Fig. 30 S
    RDY1
    Output Operation
    Fig. 31 S
    RDY1
    Input Operation (internal synchronous clock)
    S
    RDY1
    S
    CLK1
    Write to serial
    I/O1 register
    S
    RDY1
    S
    CLK1
    S
    OUT1
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