參數(shù)資料
型號(hào): M38B48E7H-XXXXFP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù): 51/78頁(yè)
文件大小: 1214K
代理商: M38B48E7H-XXXXFP
51
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
A-D CONVERTER
The 38B4 group has a 10-bit A-D converter. The A-D converter per-
forms successive approximation conversion.
[A-D Conversion Register] AD
One of these registers is a high-order register, and the other is a low-
order register. The high-order 8 bits of a conversion result is stored
in the A-D conversion register (high-order) (address 0034
16
), and
the low-order 2 bits of the same result are stored in bit 7 and bit 6 of
the A-D conversion register (low-order) (address 0033
16
).
During A-D conversion, do not read these registers.
[A-D Control Register] ADCON
This register controls A-D converter. Bits 3 to 0 are analog input pin
selection bits. Bit 4 is an AD conversion completion bit and “0” during
A-D conversion. This bit is set to “1” upon completion of A-D conver-
sion.
A-D conversion is started by setting “0” in this bit.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between AV
SS
and V
REF
, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports P7
7
/AN
7
–P7
0
/
AN
0
, and P6
5
/S
STB1
/AN
11
–P6
2
/S
RDY1
/AN
8
and inputs it to the com-
parator.
When port P6
4
is selected as an analog input pin, an external inter-
rupt function (INT
4
) is invalid.
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input
voltage with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
Fig. 55 Block diagram of A-D converter
conversion interrupt request bit to “1”.
Note that the comparator is constructed linked to a capacitor, so set
f(X
IN
) to at least 250 kHz during A-D conversion. Use a CPU system
clock dividing the main clock X
IN
as the internal system clock.
Fig. 54 Structure of A-D control register
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4
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/
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1
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5
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4
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5
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6
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7
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8
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P
6
2
/
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/
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3
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1
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