參數(shù)資料
型號： M38B47EBH-XXXXFP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 44/78頁
文件大小： 1214K
代理商： M38B47EBH-XXXXFP
44
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Data Setup
(1) 16-timingordinary mode
The area of addresses 0FB0
16
to 0FFF
16
are used as a
FLD automatic display RAM.
When data is stored in the FLD automatic display RAM,
the last data of FLD port P2 is stored at address 0FB0
16
,
the last data of FLD port P0 is stored at address 0FC0
16
,
the last data of FLD port P1 is stored at address 0FD0
16
,
the last data of FLD port P3 is stored at address 0FE0
16
,
and the last data of FLD port P8 is stored at address 0FF0
16
,
to assign in sequence from the last data respectively.
The first data of the FLD port P2, P0, P1, P3, and P8 is stored at
an address which adds the value of (the timing number – 1) to the
corresponding address 0FB0
16
, 0FC0
16
, 0FD0
16
, 0FE0
16
, and
0FF0
16
.
Set the FLD data pointer reload register to the value given by the
timing number – 1. “1” is always written to bits 7, 6, and 5. Note
that “0” is always read from bits 7, 6, and 5 when reading. “1” is
always set to bit 4, but this bit become written value when read-
ing.
(2) 16-timinggradation display mode
Display data setting is performed in the same way as that of the
16-timingordinary mode. Gradation display control data is ar-
ranged at an address resulting from subtracting 0050
16
from
the display data store address of each timing and pin. Bright dis-
play is performed by setting “0”, and dark display is performed by
setting “1”.
Set the FLD data pointer reload register to the value given by the
timing number – 1. “1” is always written to bits 7, 6, and 5. Note
that “0” is always read from bits 7, 6, and 5 when reading. “1” is
always set to bit 4, but this bit become written value when read-
ing.
(3) 32-timing mode
The area of addresses 0F60
16
to 0FFF
16
are used as a FLD au-
tomatic display RAM. When data is stored in the FLD automatic
display RAM, the last data of FLD port P2 is stored at address
0F60
16
, the last data of FLD port P0 is stored at address 0F80
16
,
the last data of FLD port P1 is stored at address 0FA0
16
,
the last data of FLD port P3 is stored at address 0FC0
16
,
and the last data of FLD port P8 is stored at address 0FE0
16
,
to assign in sequence from the last data respectively.
The first data of the FLD port P2, P0, P1, P3, and P8 is stored
at an address which adds the value of (the timing number – 1)
to the corresponding address 0F60
16
, 0F80
16
, 0FA0
16
, 0FC0
16
,
and 0FE0
16
.
Set the FLD data pointer reload register to the value given by
the timing number –1. “1” is always written to bits 7, 6, and 5.
Note that “0” is always read from bits 7, 6, and 5 when reading.
Fig. 46 Example of using FLD automatic display RAM in
16-timingordinary mode
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