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| 型號(hào)： | M38B43EDH-XXXXFP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 55/78頁(yè) |
| 文件大?。?/td> | 1214K |
| 代理商： | M38B43EDH-XXXXFP |
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55
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
INTERRUPT INTERVAL DETERMINATION
FUNCTION
The 38B4 group has an interrupt interval determination circuit.
This interrupt interval determination circuit has an 8-bit binary up
counter. Using this counter, it determines a duration of time from the
rising edge (falling edge) of an input signal pulse on the P4
7
/INT
2
pin
to the rising edge (falling edge) of the signal pulse that is input next.
How to determine the interrupt interval is described below.
1. Enable the INT
2
interrupt by setting bit 2 of the interrupt control
register 1 (address 003E
16
). Select the rising interval or falling
interval by setting bit 2 of the interrupt edge selection register
(address 003A
16
).
2. Set bit 0 of the interrupt interval determination control register
(address 0031
16
) to “1” (interrupt interval determination operat-
ing).
3. Select the sampling clock of 8-bit binary up counter by setting bit
1 of the interrupt interval determination control register. When
writing “0”, f(X
IN
)/128 is selected (the sampling interval: 32 μs at
f(X
IN
) = 4.19 MHz); when “1”, f(X
IN
)/256 is selected (the sampling
interval: 64 μs at f(X
IN
) = 4.19 MHz).
4. When the signal of polarity which is set on the INT
2
pin (rising or
falling edge) is input, the 8-bit binary up counter starts counting up
of the selected counter sampling clock.
5. When the signal of polarity above 4 is input again, the value of the
8-bit binary up counter is transferred to the interrupt interval
determination register (address 0030
16
), and the remote control
interrupt request occurs. Immediately after that, the 8-bit binary
up counter continues to count up again from “00
16
”.
6. When count value reaches “FF
16
”, the 8-bit binary up counter stops
counting up. Then, simultaneously when the next counter sam-
pling clock is input, the counter sets value “FF
16
” to the interrupt
interval determination register to generate the counter overflow
interrupt request.
Fig. 60 Interrupt interval determination circuit block diagram
Noise Filter
The P4
7
/INT
2
pin builds in the noise filter.
The noise filter operation is described below.
1. Select the sampling clock of the input signal with bits 2 and 3 of
the interrupt interval determination control register. When not
using the noise filter, set “00”.
2. The P4
7
/INT
2
input signal is sampled in synchronization with the
selected clock. When sampling the same level signal in a series
of three sampling, the signal is recognized as the interrupt signal,
and the interrupt request occurs.
When setting bit 4 of interrupt interval determination control
register to “1”, the interrupt request can occur at both rising and
falling edges.
When using the noise filter, set the minimum pulse width of the
INT
2
input signal to 3 cycles or more of the sample clock.
Note:
In the low-speed mode (CM
7
= 1), the interrupt interval deter-
mination function cannot operate.
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