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參數(shù)資料
| 型號： | M38B42E9H-XXXXFP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 50/78頁 |
| 文件大?。?/td> | 1214K |
| 代理商： | M38B42E9H-XXXXFP |
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50
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
P8
4
to P8
7
FLD Output Reverse Function
P8
4
to P8
7
are provided with a function to reverse the polarity of the
FLD output. This function is useful in adjusting the polarity when
using an externally installed driver.
The output polarity can be reversed by setting “1” to bit 0 of the port
P8 FLD output control register.
P8
4
to P8
7
Toff Invalid Function
P8
4
to P8
7
can output waveform in which Toff is invalid, when P8
4
to
P8
7
is selected FLD ports (See Figure 52).
The function is useful when using a 4 bits
→
16 bits decoder. The Toff
can be invalid by setting “1” to bit 2 of the port P8FLD output control
register (address 0EFC
16
).
P8
4
to P8
7
Output Delay Function
P8
4
to P8
7
can output waveform in which is delayed for 16
μ
s, when
selecting FLD port and selecting Toff invalid function (See Figure
52). When using a 4 bits
→
16 bits decoder, the function can be use-
ful for prevention of leak radiation caused by phase discrepancy be-
tween segment output waveform and digit output waveform. This func-
tion can be set by setting “1” to bit 3 of the port P8FLD output control
register (address 0EFC
16
).
Dimmer Signal Output Function
P6
3
can output the dimmer signal. When using a 4 bits
→
16 bits
decoder, the dimmer signal can be used as a control signal for a 4
bits
→
16 bits decoder. When using M35501FP, the dimmer signal
can be used as the CLK signal. The dimmer signal can be output by
setting “1” to bit 4 of the port P8FLD output control register (address
0EFC
16
).
Fig. 52 P8
4
to P8
7
FLD output waveform
Toff2 Control Bit
The value of the Toff2 time set register is valid when gradation dis-
play mode is selected. The FLD ports output (set) the data of display
RAM at the end of the Toff1 time and output “0” (reset) at the end of
the Toff2 time, when bit 7 of the port P8FLD output control register is
“0”.
The FLD ports output (set) the data of display RAM at the end of the
Toff2 time and output “0” (reset) at the end of Tdisp time, when bit 7
of the port P8FLD output control register is “1”.
Fig. 53 Structure of port P8 FLD output control register
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| M38B47E9H-XXXXFP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M38B42EAH-XXXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38B42EBH-XXXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38B42ECH-XXXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38B42EDH-XXXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38B42EEH-XXXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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