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參數(shù)資料
| 型號： | M38869FFAHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 350/379頁 |
| 文件大?。?/td> | 4123K |
| 代理商： | M38869FFAHP |
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HARDWARE
1-48
3886 Group User’s Manual
Bit 4: SCL pin Low hold bit (PIN)
This bit generates an interrupt request signal. Each time 1-byte
data is transmitted, the PIN bit changes from “1” to “0.” At the
same time, an interrupt request signal occurs to the CPU. The PIN
bit is set to “0” in synchronization with a falling of the last clock (in-
cluding the ACK clock) of an internal clock and an interrupt
request signal occurs in synchronization with a falling of the PIN
bit. When the PIN bit is “0,” the SCL is kept in the “0” state and
clock generation is disabled. Figure 42 shows an interrupt request
signal generating timing chart.
The PIN bit is set to “1” in one of the following conditions:
Executing a write instruction to the I2C data shift register (ad-
dress 001216). (This is the only condition which the prohibition of
the internal clock is released and data can be communicated ex-
cept for the start condition detection.)
When the ES0 bit is “0”
At reset
When writing “1” to the PIN bit by software
The conditions in which the PIN bit is set to “0” are shown below:
Immediately after completion of 1-byte data transmission (includ-
ing when arbitration lost is detected)
Immediately after completion of 1-byte data reception
In the slave reception mode, with ALS = “0” and immediately af-
ter completion of slave address agreement or general call
address reception
In the slave reception mode, with ALS = “1” and immediately af-
ter completion of address data reception
Bit 5: Bus busy flag (BB)
This bit indicates the status of use of the bus system. When this
bit is set to “0,” this bus system is not busy and a START condition
can be generated. The BB flag is set/reset by the SCL, SDA pins in-
put signal regardless of master/slave. This flag is set to “1” by
detecting the start condition, and is set to “0” by detecting the stop
condition. The condition of these detecting is set by the start/stop
condition setting bits (SSC4–SSC0) of the I2C start/stop condition
control register (address 001716). When the ES0 bit (bit 3) of the
I2C control register (address 001516) is “0” or reset, the BB flag is
set to “0.”
For the writing function to the BB flag, refer to the sections
“START Condition Generating Method” and “STOP Condition Gen-
erating Method” described later.
[I2C Status Register (S1)] 001416
The I2C status register (address 001416) controls the I2C-BUS in-
terface status. The low-order 4 bits are read-only bits and the
high-order 4 bits can be read out and written to.
Set “00002” to the low-order 4 bits, because these bits become the
reserved bits at writing.
Bit 0: Last receive bit (LRB)
This bit stores the last bit value of received data and can also be
used for ACK receive confirmation. If ACK is returned when an
ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned,
this bit is set to “1.” Except in the ACK mode, the last bit value of
received data is input. The state of this bit is changed from “1” to
“0” by executing a write instruction to the I2C data shift register
(address 001216).
Bit 1: General call detecting flag (AD0)
When the ALS bit is “0,” this bit is set to “1” when a general call
whose address data is all “0” is received in the slave mode. By a
general call of the master device, every slave device receives con-
trol data after the general call. The AD0 bit is set to “0” by
detecting the STOP condition or START condition, or reset.
General call: The master transmits the general call address “0016” to all
slaves.
Bit 2: Slave address comparison flag (AAS)
This flag indicates a comparison result of address data when the
ALS bit is “0”.
In the slave receive mode, when the 7-bit addressing format is
selected, this bit is set to “1” in one of the following conditions:
The address data immediately after occurrence of a START
condition agrees with the slave address stored in the high-or-
der 7 bits of the I2C address register (address 001316).
A general call is received.
In the slave reception mode, when the 10-bit addressing format
is selected, this bit is set to “1” with the following condition:
When the address data is compared with the I2C address reg-
ister (8 bits consisting of slave address and RWB bit), the first
bytes agree.
This bit is set to “0” by executing a write instruction to the I2C
data shift register (address 001216) when ES0 is set to “1” or
reset.
Bit 3: Arbitration lost detecting flag (AL)
In the master transmission mode, when the SDA is made “L” by
any other device, arbitration is judged to have been lost, so that
this bit is set to “1.” At the same time, the TRX bit is set to “0,” so
that immediately after transmission of the byte whose arbitration
was lost is completed, the MST bit is set to “0.” The arbitration lost
can be detected only in the master transmission mode. When ar-
bitration is lost during slave address transmission, the TRX bit is
set to “0” and the reception mode is set. Consequently, it becomes
possible to detect the agreement of its own slave address and ad-
dress data transmitted by another master device.
Arbitration lost :The status in which communication as a master is dis-
abled.
FUNCTIONAL DESCRIPTION
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| M38869FFAHP#UU | 功能描述:IC 740/3886 MCU FLASH 80LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 產(chǎn)品培訓(xùn)模塊:CAN Basics Part-1 CAN Basics Part-2 Electromagnetic Noise Reduction Techniques Part 1 M16C Product Overview Part 1 M16C Product Overview Part 2 標準包裝:1 系列:M16C™ M32C/80/87 核心處理器:M32C/80 芯體尺寸:16/32-位 速度:32MHz 連通性:EBI/EMI，I²C，IEBus，IrDA，SIO，UART/USART 外圍設(shè)備:DMA，POR，PWM，WDT 輸入/輸出數(shù):121 程序存儲器容量:384KB（384K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:24K x 8 電壓 - 電源 (Vcc/Vdd):3 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 34x10b，D/A 2x8b 振蕩器型:內(nèi)部 工作溫度:-20°C ~ 85°C 封裝/外殼:144-LQFP 包裝:托盤 產(chǎn)品目錄頁面:749 (CN2011-ZH PDF) 配用:R0K330879S001BE-ND - KIT DEV RSK M32C/87 |
| M38869FF-XXXHP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38869M1-XXXHP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38869M2-XXXHP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38869M3-XXXHP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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