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參數(shù)資料
| 型號(hào)： | M38867M8A-A11HP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 20/110頁 |
| 文件大?。?/td> | 1601K |
| 代理商： | M38867M8A-A11HP |
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20
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Interrupt Request
Generating Conditions
Remarks
Interrupt Source
Low
FFFC
16
FFFA
16
FFF8
16
FFF6
16
FFF4
16
FFF2
16
FFF0
16
FFEE
16
FFEC
16
FFEA
16
FFE8
16
FFE6
16
FFE4
16
FFE2
16
FFE0
16
FFDE
16
FFDC
16
High
FFFD
16
FFFB
16
FFF9
16
FFF7
16
FFF5
16
FFF3
16
FFF1
16
FFEF
16
FFED
16
FFEB
16
FFE9
16
FFE7
16
FFE5
16
FFE3
16
FFE1
16
FFDF
16
FFDD
16
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Table 6 Interrupt vector addresses and priority
Notes 1:
Vector addresses contain interrupt jump destination addresses.
2:
Reset function in the same way as an interrupt with the highest priority.
Vector Addresses (Note 1)
Reset (Note 2)
INT
0
Input buffer full
(IBF)
INT
1
Output buffer
empty (OBE)
Serial I/O1
reception
Serial I/O1
transmission
S
CL
, S
DA
Timer X
Timer Y
Timer 1
Timer 2
CNTR
0
S
CL
, S
DA
CNTR
1
Key-on wake-up
Serial I/O2
I
2
C
INT
2
I
2
C
INT
3
INT
4
A-D converter
Key-on wake-up
BRK instruction
At reset
At detection of either rising or
falling edge of INT
0
input
At input data bus buffer writing
At detection of either rising or
falling edge of INT
1
input
At output data bus buffer read-
ing
At completion of serial I/O1 data
reception
At completion of serial I/O1
transfer shift or when transmis-
sion buffer is empty
At detection of either rising or
falling edge of S
CL
or S
DA
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At detection of either rising or
falling edge of CNTR
0
input
At detection of either rising or
falling edge of S
CL
or S
DA
At detection of either rising or
falling edge of CNTR
1
input
At falling of port P3 (at input) in-
put logical level AND
At completion of serial I/O2 data
transfer
At completion of data transfer
At detection of either rising or
falling edge of INT
2
input
At completion of data transfer
At detection of either rising or
falling edge of INT
3
input
At detection of either rising or
falling edge of INT
4
input
At completion of A-D conversion
At falling of port P3 (at input) in-
put logical level AND
At BRK instruction execution
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
External interrupt
(active edge selectable)
STP release timer underflow
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (falling valid)
Valid when serial I/O2 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (falling valid)
Non-maskable software interrupt
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